Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	73452	1			T1	2		T2	2		T3	1
all_pins[1]	73452	1			T1	2		T2	2		T3	1
all_pins[2]	73452	1			T1	2		T2	2		T3	1
all_pins[3]	73452	1			T1	2		T2	2		T3	1
all_pins[4]	73452	1			T1	2		T2	2		T3	1
all_pins[5]	73452	1			T1	2		T2	2		T3	1
all_pins[6]	73452	1			T1	2		T2	2		T3	1
all_pins[7]	73452	1			T1	2		T2	2		T3	1
all_pins[8]	73452	1			T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	627336	1			T1	18		T2	18		T3	7
values[0x1]	33732	1			T3	2		T7	2		T11	9
transitions[0x0=>0x1]	27541	1			T3	1		T7	1		T11	7
transitions[0x1=>0x0]	27363	1			T3	1		T7	1		T11	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	57747	1			T1	2		T2	2		T5	2
all_pins[0]	values[0x1]	15705	1			T3	1		T7	1		T11	3
all_pins[0]	transitions[0x0=>0x1]	15136	1			T3	1		T7	1		T11	3
all_pins[0]	transitions[0x1=>0x0]	944	1			T18	9		T86	8		T30	1
all_pins[1]	values[0x0]	71939	1			T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	1513	1			T13	2		T19	3		T18	9
all_pins[1]	transitions[0x0=>0x1]	1416	1			T13	2		T19	2		T18	9
all_pins[1]	transitions[0x1=>0x0]	2027	1			T12	1		T21	2		T17	2
all_pins[2]	values[0x0]	71328	1			T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	2124	1			T12	1		T21	2		T17	2
all_pins[2]	transitions[0x0=>0x1]	2066	1			T12	1		T21	2		T17	2
all_pins[2]	transitions[0x1=>0x0]	249	1			T11	2		T19	1		T18	1
all_pins[3]	values[0x0]	73145	1			T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	307	1			T11	2		T19	3		T18	1
all_pins[3]	transitions[0x0=>0x1]	261	1			T11	2		T19	3		T18	1
all_pins[3]	transitions[0x1=>0x0]	327	1			T19	1		T18	5		T30	2
all_pins[4]	values[0x0]	73079	1			T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	373	1			T19	1		T18	5		T30	3
all_pins[4]	transitions[0x0=>0x1]	314	1			T19	1		T18	4		T30	3
all_pins[4]	transitions[0x1=>0x0]	146	1			T13	1		T19	4		T18	1
all_pins[5]	values[0x0]	73247	1			T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	205	1			T13	1		T19	4		T18	2
all_pins[5]	transitions[0x0=>0x1]	164	1			T13	1		T19	4		T18	2
all_pins[5]	transitions[0x1=>0x0]	730	1			T11	1		T12	1		T21	2
all_pins[6]	values[0x0]	72681	1			T1	2		T2	2		T3	1
all_pins[6]	values[0x1]	771	1			T11	1		T12	1		T21	2
all_pins[6]	transitions[0x0=>0x1]	711	1			T11	1		T12	1		T21	2
all_pins[6]	transitions[0x1=>0x0]	267	1			T19	1		T30	4		T116	2
all_pins[7]	values[0x0]	73125	1			T1	2		T2	2		T3	1
all_pins[7]	values[0x1]	327	1			T19	1		T30	4		T116	2
all_pins[7]	transitions[0x0=>0x1]	193	1			T30	3		T116	1		T106	1
all_pins[7]	transitions[0x1=>0x0]	12273	1			T3	1		T7	1		T11	3
all_pins[8]	values[0x0]	61045	1			T1	2		T2	2		T5	2
all_pins[8]	values[0x1]	12407	1			T3	1		T7	1		T11	3
all_pins[8]	transitions[0x0=>0x1]	7280	1			T11	1		T13	18		T21	1
all_pins[8]	transitions[0x1=>0x0]	10400	1			T12	1		T13	27		T44	1