Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5236168	1			T3	1		T11	5		T12	5
all_levels[1]	1337914	1			T13	433		T21	2		T17	9
all_levels[2]	216770	1			T12	1		T13	774		T17	4
all_levels[3]	158233	1			T21	6		T17	8		T83	10
all_levels[4]	225620	1			T11	3		T12	1		T83	7611
all_levels[5]	172265	1			T19	3		T37	1		T42	536
all_levels[6]	166844	1			T17	2		T19	4		T42	544
all_levels[7]	186877	1			T12	3		T21	1		T17	2
all_levels[8]	180510	1			T17	2		T19	4		T42	531
all_levels[9]	172382	1			T11	1		T17	6		T19	3
all_levels[10]	169246	1			T17	9		T19	4		T42	544
all_levels[11]	138461	1			T21	51		T44	2		T19	6
all_levels[12]	139223	1			T12	1		T19	2		T37	1
all_levels[13]	137586	1			T19	3		T42	544		T43	2
all_levels[14]	137185	1			T11	2		T12	1		T19	4
all_levels[15]	134410	1			T17	3		T19	4		T37	2
all_levels[16]	283496	1			T11	2		T12	1		T17	3
all_levels[17]	158239	1			T17	5		T19	3		T42	544
all_levels[18]	127547	1			T12	1		T17	6		T19	3
all_levels[19]	136321	1			T17	2		T19	3		T37	1
all_levels[20]	236717	1			T17	2		T19	3		T42	539
all_levels[21]	417358	1			T12	1		T17	4		T19	3
all_levels[22]	128155	1			T17	3		T19	2		T42	544
all_levels[23]	275568	1			T12	1		T17	3		T44	2
all_levels[24]	131563	1			T12	2		T17	1		T44	2
all_levels[25]	122268	1			T12	2		T17	8		T19	3
all_levels[26]	122445	1			T17	7		T19	2		T42	546
all_levels[27]	117087	1			T17	5		T19	3		T42	2236
all_levels[28]	110842	1			T17	2		T19	3		T42	544
all_levels[29]	165477	1			T11	4		T17	2		T19	3
all_levels[30]	131651	1			T17	5		T19	2		T42	532
all_levels[31]	435241	1			T17	7		T19	462		T42	684
all_levels[32]	8583297	1			T11	10		T12	18		T17	23

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20589153

1

T11

26

T12

37

T13

1196

auto[1]

3813

1

T3

1

T11

1

T12

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5234000	1			T11	4		T12	5		T13	2
all_levels[0]	auto[1]	2168	1			T3	1		T11	1		T13	5
all_levels[1]	auto[0]	1337665	1			T13	420		T21	2		T17	9
all_levels[1]	auto[1]	249	1			T13	13		T37	2		T30	1
all_levels[2]	auto[0]	216738	1			T12	1		T13	774		T17	4
all_levels[2]	auto[1]	32	1			T383	1		T384	2		T385	2
all_levels[3]	auto[0]	158121	1			T21	6		T17	8		T83	2
all_levels[3]	auto[1]	112	1			T83	8		T86	2		T272	2
all_levels[4]	auto[0]	225595	1			T11	3		T12	1		T83	7611
all_levels[4]	auto[1]	25	1			T334	1		T148	3		T184	1
all_levels[5]	auto[0]	172234	1			T19	3		T37	1		T42	536
all_levels[5]	auto[1]	31	1			T119	2		T327	1		T386	1
all_levels[6]	auto[0]	166825	1			T17	2		T19	4		T42	544
all_levels[6]	auto[1]	19	1			T316	1		T387	1		T327	1
all_levels[7]	auto[0]	186757	1			T12	3		T21	1		T17	2
all_levels[7]	auto[1]	120	1			T43	1		T85	16		T273	1
all_levels[8]	auto[0]	180476	1			T17	2		T19	4		T42	531
all_levels[8]	auto[1]	34	1			T103	2		T335	1		T350	1
all_levels[9]	auto[0]	172358	1			T11	1		T17	6		T19	3
all_levels[9]	auto[1]	24	1			T101	1		T86	1		T368	1
all_levels[10]	auto[0]	169211	1			T17	9		T19	4		T42	544
all_levels[10]	auto[1]	35	1			T285	1		T152	1		T364	1
all_levels[11]	auto[0]	138434	1			T21	51		T44	2		T19	6
all_levels[11]	auto[1]	27	1			T112	1		T182	2		T388	1
all_levels[12]	auto[0]	139193	1			T12	1		T19	2		T37	1
all_levels[12]	auto[1]	30	1			T103	2		T389	1		T390	2
all_levels[13]	auto[0]	137549	1			T19	3		T42	544		T43	2
all_levels[13]	auto[1]	37	1			T126	1		T391	1		T200	4
all_levels[14]	auto[0]	137159	1			T11	2		T12	1		T19	4
all_levels[14]	auto[1]	26	1			T88	1		T174	2		T392	1
all_levels[15]	auto[0]	134294	1			T17	3		T19	4		T37	2
all_levels[15]	auto[1]	116	1			T85	6		T272	16		T345	9
all_levels[16]	auto[0]	283479	1			T11	2		T12	1		T17	3
all_levels[16]	auto[1]	17	1			T293	1		T351	1		T296	1
all_levels[17]	auto[0]	158218	1			T17	5		T19	3		T42	544
all_levels[17]	auto[1]	21	1			T310	1		T304	1		T328	1
all_levels[18]	auto[0]	127533	1			T12	1		T17	6		T19	3
all_levels[18]	auto[1]	14	1			T90	1		T393	1		T394	1
all_levels[19]	auto[0]	136304	1			T17	2		T19	3		T37	1
all_levels[19]	auto[1]	17	1			T92	1		T314	1		T120	1
all_levels[20]	auto[0]	236700	1			T17	2		T19	3		T42	539
all_levels[20]	auto[1]	17	1			T256	1		T395	2		T149	1
all_levels[21]	auto[0]	417336	1			T12	1		T17	4		T19	3
all_levels[21]	auto[1]	22	1			T103	2		T102	1		T290	1
all_levels[22]	auto[0]	128142	1			T17	3		T19	2		T42	544
all_levels[22]	auto[1]	13	1			T396	1		T397	1		T213	2
all_levels[23]	auto[0]	275536	1			T12	1		T17	3		T44	2
all_levels[23]	auto[1]	32	1			T115	3		T130	1		T398	1
all_levels[24]	auto[0]	131559	1			T12	2		T17	1		T44	2
all_levels[24]	auto[1]	4	1			T141	1		T399	1		T146	1
all_levels[25]	auto[0]	122257	1			T12	2		T17	8		T19	3
all_levels[25]	auto[1]	11	1			T400	1		T401	1		T402	1
all_levels[26]	auto[0]	122429	1			T17	7		T19	2		T42	546
all_levels[26]	auto[1]	16	1			T122	1		T94	2		T403	1
all_levels[27]	auto[0]	117073	1			T17	5		T19	3		T42	2235
all_levels[27]	auto[1]	14	1			T42	1		T183	2		T404	1
all_levels[28]	auto[0]	110825	1			T17	2		T19	3		T42	544
all_levels[28]	auto[1]	17	1			T103	1		T283	1		T154	1
all_levels[29]	auto[0]	165462	1			T11	4		T17	2		T19	3
all_levels[29]	auto[1]	15	1			T111	1		T221	1		T394	1
all_levels[30]	auto[0]	131631	1			T17	5		T19	2		T42	532
all_levels[30]	auto[1]	20	1			T184	2		T142	1		T403	1
all_levels[31]	auto[0]	435228	1			T17	7		T19	462		T42	684
all_levels[31]	auto[1]	13	1			T142	3		T405	1		T406	1
all_levels[32]	auto[0]	8582832	1			T11	10		T12	17		T17	23
all_levels[32]	auto[1]	465	1			T12	1		T67	1		T105	1