Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	777	1			T19	11		T30	4		T34	7
all_values[1]	777	1			T19	11		T30	4		T34	7
all_values[2]	777	1			T19	11		T30	4		T34	7
all_values[3]	777	1			T19	11		T30	4		T34	7
all_values[4]	777	1			T19	11		T30	4		T34	7
all_values[5]	777	1			T19	11		T30	4		T34	7
all_values[6]	777	1			T19	11		T30	4		T34	7
all_values[7]	777	1			T19	11		T30	4		T34	7
all_values[8]	777	1			T19	11		T30	4		T34	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3826

1

T19

59

T30

18

T34

45

auto[1]

3167

1

T19

40

T30

18

T34

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2266

1

T19

28

T30

11

T34

19

auto[1]

4727

1

T19

71

T30

25

T34

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4115

1

T19

54

T30

25

T34

32

auto[1]

2878

1

T19

45

T30

11

T34

31

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	237	1			T19	4		T30	2		T34	2
all_values[0]	auto[0]	auto[1]	auto[1]	219	1			T19	4		T30	1		T66	1
all_values[0]	auto[1]	auto[0]	auto[1]	168	1			T19	1		T30	1		T34	4
all_values[0]	auto[1]	auto[1]	auto[1]	153	1			T19	2		T34	1		T66	3
all_values[1]	auto[0]	auto[0]	auto[0]	237	1			T19	5		T30	2		T34	5
all_values[1]	auto[0]	auto[1]	auto[0]	222	1			T19	1		T66	2		T36	1
all_values[1]	auto[1]	auto[0]	auto[1]	177	1			T19	2		T34	2		T66	2
all_values[1]	auto[1]	auto[1]	auto[1]	141	1			T19	3		T30	2		T36	1
all_values[2]	auto[0]	auto[0]	auto[0]	182	1			T19	2		T30	3		T34	4
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T19	2		T36	1		T97	1
all_values[2]	auto[0]	auto[1]	auto[0]	140	1			T30	1		T36	1		T97	3
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T19	1		T66	1		T97	1
all_values[2]	auto[1]	auto[0]	auto[1]	162	1			T19	4		T34	2		T36	1
all_values[2]	auto[1]	auto[1]	auto[1]	134	1			T19	2		T34	1		T66	4
all_values[3]	auto[0]	auto[0]	auto[0]	169	1			T30	1		T34	1		T66	3
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T19	3		T30	1		T34	1
all_values[3]	auto[0]	auto[1]	auto[0]	132	1			T19	1		T36	1		T97	1
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T34	1		T66	1		T97	1
all_values[3]	auto[1]	auto[0]	auto[1]	172	1			T19	3		T34	3		T66	1
all_values[3]	auto[1]	auto[1]	auto[1]	154	1			T19	4		T30	2		T34	1
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T19	1		T30	1		T66	2
all_values[4]	auto[0]	auto[0]	auto[1]	99	1			T19	1		T34	1		T97	2
all_values[4]	auto[0]	auto[1]	auto[0]	124	1			T19	4		T36	3		T97	1
all_values[4]	auto[0]	auto[1]	auto[1]	70	1			T30	2		T34	1		T66	1
all_values[4]	auto[1]	auto[0]	auto[1]	179	1			T19	4		T34	2		T66	1
all_values[4]	auto[1]	auto[1]	auto[1]	140	1			T19	1		T30	1		T34	3
all_values[5]	auto[0]	auto[0]	auto[0]	184	1			T19	2		T30	1		T34	1
all_values[5]	auto[0]	auto[0]	auto[1]	76	1			T19	2		T30	1		T34	1
all_values[5]	auto[0]	auto[1]	auto[0]	122	1			T30	1		T34	1		T66	3
all_values[5]	auto[0]	auto[1]	auto[1]	77	1			T19	2		T34	1		T97	1
all_values[5]	auto[1]	auto[0]	auto[1]	165	1			T19	4		T34	2		T36	1
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T19	1		T30	1		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	152	1			T19	5		T34	4		T66	1
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T30	1		T66	2		T36	1
all_values[6]	auto[0]	auto[1]	auto[0]	137	1			T19	2		T30	1		T34	1
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T34	1		T66	1		T97	1
all_values[6]	auto[1]	auto[0]	auto[1]	178	1			T19	2		T30	1		T66	1
all_values[6]	auto[1]	auto[1]	auto[1]	149	1			T19	2		T30	1		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	175	1			T19	1		T34	2		T66	1
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T19	1		T34	2		T36	2
all_values[7]	auto[0]	auto[1]	auto[0]	125	1			T19	4		T36	2		T97	1
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T30	3		T66	2		T78	2
all_values[7]	auto[1]	auto[0]	auto[1]	186	1			T19	4		T30	1		T34	3
all_values[7]	auto[1]	auto[1]	auto[1]	124	1			T19	1		T66	4		T97	3
all_values[8]	auto[0]	auto[0]	auto[1]	243	1			T19	4		T30	1		T34	1
all_values[8]	auto[0]	auto[1]	auto[1]	191	1			T19	2		T30	2		T34	1
all_values[8]	auto[1]	auto[0]	auto[1]	197	1			T19	2		T30	1		T34	2
all_values[8]	auto[1]	auto[1]	auto[1]	146	1			T19	3		T34	3		T66	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal