Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	79196	1			T1	2		T2	1		T3	2
all_values[1]	79196	1			T1	2		T2	1		T3	2
all_values[2]	79196	1			T1	2		T2	1		T3	2
all_values[3]	79196	1			T1	2		T2	1		T3	2
all_values[4]	79196	1			T1	2		T2	1		T3	2
all_values[5]	79196	1			T1	2		T2	1		T3	2
all_values[6]	79196	1			T1	2		T2	1		T3	2
all_values[7]	79196	1			T1	2		T2	1		T3	2
all_values[8]	79196	1			T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

359834

1

T1

18

T2

4

T3

18

auto[1]

352930

1

T2

5

T4

3

T5

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

638550

1

T1

13

T2

7

T3

13

auto[1]

74214

1

T1

5

T2

2

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	22599	1			T10	3		T11	1		T12	3
all_values[0]	auto[0]	auto[1]	20035	1			T1	2		T3	2		T7	1
all_values[0]	auto[1]	auto[0]	19745	1			T5	2		T13	1		T31	2
all_values[0]	auto[1]	auto[1]	16817	1			T2	1		T4	1		T5	3
all_values[1]	auto[0]	auto[0]	35264	1			T1	2		T2	1		T3	2
all_values[1]	auto[0]	auto[1]	1326	1			T13	7		T94	11		T118	1
all_values[1]	auto[1]	auto[0]	41399	1			T7	4		T10	6		T11	1
all_values[1]	auto[1]	auto[1]	1207	1			T10	1		T97	3		T16	8
all_values[2]	auto[0]	auto[0]	40580	1			T1	1		T3	1		T5	1
all_values[2]	auto[0]	auto[1]	2259	1			T1	1		T3	1		T5	1
all_values[2]	auto[1]	auto[0]	34409	1			T2	1		T4	1		T5	3
all_values[2]	auto[1]	auto[1]	1948	1			T7	3		T10	3		T11	2
all_values[3]	auto[0]	auto[0]	38338	1			T1	2		T3	2		T4	1
all_values[3]	auto[0]	auto[1]	278	1			T14	4		T15	1		T16	2
all_values[3]	auto[1]	auto[0]	40324	1			T2	1		T7	5		T10	1
all_values[3]	auto[1]	auto[1]	256	1			T10	3		T14	2		T125	1
all_values[4]	auto[0]	auto[0]	38957	1			T1	2		T3	2		T4	1
all_values[4]	auto[0]	auto[1]	316	1			T20	7		T43	3		T105	2
all_values[4]	auto[1]	auto[0]	39608	1			T2	1		T5	5		T7	8
all_values[4]	auto[1]	auto[1]	315	1			T10	4		T19	17		T20	9
all_values[5]	auto[0]	auto[0]	41433	1			T1	2		T3	2		T9	2
all_values[5]	auto[0]	auto[1]	144	1			T43	3		T73	2		T107	3
all_values[5]	auto[1]	auto[0]	37467	1			T2	1		T4	1		T5	5
all_values[5]	auto[1]	auto[1]	152	1			T10	4		T43	4		T72	1
all_values[6]	auto[0]	auto[0]	41633	1			T1	2		T2	1		T3	2
all_values[6]	auto[0]	auto[1]	154	1			T10	2		T43	4		T72	1
all_values[6]	auto[1]	auto[0]	37263	1			T5	2		T7	3		T11	1
all_values[6]	auto[1]	auto[1]	146	1			T10	2		T43	5		T72	1
all_values[7]	auto[0]	auto[0]	37299	1			T1	2		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	294	1			T10	3		T126	1		T116	2
all_values[7]	auto[1]	auto[0]	41246	1			T5	5		T7	7		T10	3
all_values[7]	auto[1]	auto[1]	357	1			T10	1		T30	1		T43	4
all_values[8]	auto[0]	auto[0]	25303	1			T5	2		T13	1		T12	1
all_values[8]	auto[0]	auto[1]	13622	1			T1	2		T2	1		T3	2
all_values[8]	auto[1]	auto[0]	25683	1			T7	1		T10	3		T11	1
all_values[8]	auto[1]	auto[1]	14588	1			T10	1		T11	3		T13	10