Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2542

1

T1

1

T2

1

T3

1

auto[UartRx]

2542

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4445	1			T1	2		T2	2		T3	2
values[1]	46	1			T32	1		T44	1		T46	1
values[2]	47	1			T42	1		T44	1		T45	1
values[3]	57	1			T31	1		T44	1		T45	1
values[4]	47	1			T10	1		T40	1		T41	1
values[5]	54	1			T42	1		T143	1		T87	1
values[6]	56	1			T31	1		T143	1		T111	1
values[7]	81	1			T31	2		T40	1		T41	1
values[8]	61	1			T42	2		T44	2		T143	1
values[9]	57	1			T40	1		T143	1		T72	2
values[10]	86	1			T10	3		T31	1		T32	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2310	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	21	1			T44	1		T72	1		T111	1
auto[UartTx]	values[2]	16	1			T44	1		T394	1		T395	1
auto[UartTx]	values[3]	24	1			T31	1		T45	1		T46	1
auto[UartTx]	values[4]	16	1			T42	2		T72	1		T88	1
auto[UartTx]	values[5]	23	1			T87	1		T396	1		T92	1
auto[UartTx]	values[6]	20	1			T143	1		T111	1		T396	1
auto[UartTx]	values[7]	28	1			T31	2		T40	1		T41	1
auto[UartTx]	values[8]	22	1			T42	1		T44	2		T87	1
auto[UartTx]	values[9]	19	1			T40	1		T143	1		T88	1
auto[UartTx]	values[10]	26	1			T41	1		T42	1		T375	2
auto[UartRx]	values[0]	2135	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	25	1			T32	1		T46	1		T72	1
auto[UartRx]	values[2]	31	1			T42	1		T45	1		T87	1
auto[UartRx]	values[3]	33	1			T44	1		T143	1		T317	2
auto[UartRx]	values[4]	31	1			T10	1		T40	1		T41	1
auto[UartRx]	values[5]	31	1			T42	1		T143	1		T111	1
auto[UartRx]	values[6]	36	1			T31	1		T110	1		T397	1
auto[UartRx]	values[7]	53	1			T44	3		T46	1		T317	1
auto[UartRx]	values[8]	39	1			T42	1		T143	1		T317	1
auto[UartRx]	values[9]	38	1			T72	2		T87	1		T375	1
auto[UartRx]	values[10]	60	1			T10	3		T31	1		T32	1