Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1841	1			T4	3		T10	1		T13	1
auto[BaudRate115200]	1427	1			T7	1		T10	2		T12	1
auto[BaudRate230400]	1525	1			T3	1		T5	2		T7	1
auto[BaudRate128Kbps]	1528	1			T1	1		T2	3		T9	1
auto[BaudRate256Kbps]	1704	1			T2	3		T5	4		T7	2
auto[BaudRate1Mbps]	1296	1			T3	1		T13	3		T12	3
auto[BaudRate1p5Mbps]	904	1			T1	1		T10	2		T11	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1171	1			T11	10		T12	10		T329	2
freqs[25]	965	1			T31	7		T17	20		T33	17
freqs[48]	353	1			T114	19		T290	1		T398	17
freqs[50]	330	1			T35	2		T23	2		T399	15
freqs[100]	928	1			T10	5		T27	2		T93	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	232	1			T12	1		T18	13		T135	3
auto[BaudRate9600]	freqs[25]	177	1			T31	2		T17	20		T33	4
auto[BaudRate9600]	freqs[48]	75	1			T114	1		T290	1		T398	17
auto[BaudRate9600]	freqs[50]	72	1			T35	1		T400	1		T401	11
auto[BaudRate9600]	freqs[100]	118	1			T10	1		T93	3		T94	1
auto[BaudRate115200]	freqs[24]	138	1			T12	1		T135	1		T48	1
auto[BaudRate115200]	freqs[25]	132	1			T33	5		T284	1		T303	1
auto[BaudRate115200]	freqs[48]	41	1			T114	1		T402	1		T337	1
auto[BaudRate115200]	freqs[50]	40	1			T400	1		T403	5		T358	1
auto[BaudRate115200]	freqs[100]	111	1			T10	2		T93	2		T115	1
auto[BaudRate230400]	freqs[24]	199	1			T11	3		T12	2		T48	2
auto[BaudRate230400]	freqs[25]	140	1			T364	1		T142	1		T121	1
auto[BaudRate230400]	freqs[48]	55	1			T114	4		T302	1		T173	2
auto[BaudRate230400]	freqs[50]	46	1			T399	6		T400	1		T403	2
auto[BaudRate230400]	freqs[100]	137	1			T93	2		T94	3		T115	2
auto[BaudRate128Kbps]	freqs[24]	180	1			T11	1		T135	3		T48	3
auto[BaudRate128Kbps]	freqs[25]	128	1			T31	3		T33	2		T354	1
auto[BaudRate128Kbps]	freqs[48]	50	1			T114	4		T402	1		T382	2
auto[BaudRate128Kbps]	freqs[50]	43	1			T399	3		T400	2		T403	1
auto[BaudRate128Kbps]	freqs[100]	138	1			T27	1		T93	1		T94	3
auto[BaudRate256Kbps]	freqs[24]	170	1			T11	4		T12	2		T329	2
auto[BaudRate256Kbps]	freqs[25]	158	1			T31	1		T33	1		T47	3
auto[BaudRate256Kbps]	freqs[48]	53	1			T114	5		T302	4		T366	11
auto[BaudRate256Kbps]	freqs[50]	44	1			T35	1		T23	1		T400	1
auto[BaudRate256Kbps]	freqs[100]	136	1			T94	1		T115	1		T49	1
auto[BaudRate1Mbps]	freqs[24]	179	1			T12	3		T135	2		T48	2
auto[BaudRate1Mbps]	freqs[25]	149	1			T33	3		T354	1		T47	2
auto[BaudRate1Mbps]	freqs[48]	39	1			T114	1		T302	1		T366	5
auto[BaudRate1Mbps]	freqs[50]	34	1			T399	3		T400	4		T403	1
auto[BaudRate1Mbps]	freqs[100]	129	1			T93	1		T94	1		T115	1
auto[BaudRate1p5Mbps]	freqs[25]	81	1			T31	1		T33	2		T47	2
auto[BaudRate1p5Mbps]	freqs[48]	40	1			T114	3		T302	2		T173	1
auto[BaudRate1p5Mbps]	freqs[50]	51	1			T23	1		T399	3		T404	3
auto[BaudRate1p5Mbps]	freqs[100]	159	1			T10	2		T27	1		T94	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded