Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	22738974	1			T2	1		T4	1		T5	11
all_levels[1]	160063	1			T7	1		T11	1		T13	1
all_levels[2]	2115	1			T12	1		T93	2		T94	1
all_levels[3]	877	1			T13	2		T93	2		T33	3
all_levels[4]	539	1			T7	1		T93	1		T94	1
all_levels[5]	450	1			T13	2		T93	1		T33	1
all_levels[6]	350	1			T5	2		T33	7		T114	2
all_levels[7]	258	1			T115	2		T48	1		T14	2
all_levels[8]	220	1			T13	4		T94	2		T33	4
all_levels[9]	179	1			T5	1		T11	1		T13	1
all_levels[10]	177	1			T11	1		T13	1		T93	1
all_levels[11]	153	1			T13	2		T33	1		T16	1
all_levels[12]	122	1			T5	2		T13	2		T33	2
all_levels[13]	129	1			T7	1		T94	1		T116	1
all_levels[14]	107	1			T94	1		T115	1		T117	1
all_levels[15]	93	1			T115	1		T14	1		T118	1
all_levels[16]	72	1			T116	1		T119	1		T120	1
all_levels[17]	88	1			T14	1		T15	1		T121	1
all_levels[18]	81	1			T49	1		T118	1		T122	1
all_levels[19]	57	1			T122	1		T98	1		T121	1
all_levels[20]	58	1			T115	1		T123	1		T121	2
all_levels[21]	45	1			T118	1		T98	1		T124	1
all_levels[22]	48	1			T15	1		T98	1		T117	1
all_levels[23]	57	1			T49	1		T125	1		T116	2
all_levels[24]	49	1			T115	1		T121	1		T106	1
all_levels[25]	52	1			T121	1		T106	1		T117	1
all_levels[26]	58	1			T13	1		T115	1		T126	1
all_levels[27]	46	1			T115	1		T127	1		T128	1
all_levels[28]	39	1			T119	1		T124	1		T129	1
all_levels[29]	27	1			T130	2		T131	1		T132	1
all_levels[30]	35	1			T102	2		T133	1		T134	2
all_levels[31]	32	1			T5	1		T135	5		T15	1
all_levels[32]	27	1			T12	1		T127	1		T129	2
all_levels[33]	28	1			T98	1		T103	1		T96	2
all_levels[34]	23	1			T12	1		T16	1		T119	1
all_levels[35]	22	1			T49	1		T136	2		T137	1
all_levels[36]	32	1			T15	1		T138	2		T139	1
all_levels[37]	15	1			T14	1		T106	1		T100	1
all_levels[38]	21	1			T5	1		T116	1		T98	1
all_levels[39]	21	1			T16	1		T116	1		T98	1
all_levels[40]	10	1			T16	1		T140	1		T141	1
all_levels[41]	16	1			T142	1		T143	1		T136	1
all_levels[42]	20	1			T106	3		T144	1		T136	1
all_levels[43]	9	1			T106	1		T103	1		T145	1
all_levels[44]	9	1			T146	1		T103	1		T147	1
all_levels[45]	12	1			T148	1		T96	1		T149	1
all_levels[46]	15	1			T119	1		T148	2		T150	1
all_levels[47]	13	1			T124	1		T107	1		T151	1
all_levels[48]	3	1			T152	1		T153	1		T154	1
all_levels[49]	8	1			T126	1		T155	1		T156	1
all_levels[50]	8	1			T155	1		T157	1		T96	1
all_levels[51]	9	1			T118	1		T136	1		T156	1
all_levels[52]	10	1			T13	1		T158	1		T132	1
all_levels[53]	3	1			T155	1		T96	1		T159	1
all_levels[54]	10	1			T15	1		T128	1		T160	1
all_levels[55]	11	1			T125	1		T161	2		T140	1
all_levels[56]	9	1			T140	1		T150	1		T162	1
all_levels[57]	6	1			T107	1		T149	1		T163	1
all_levels[58]	8	1			T13	1		T156	1		T164	1
all_levels[59]	7	1			T117	1		T138	1		T165	1
all_levels[60]	10	1			T138	1		T147	1		T160	1
all_levels[61]	7	1			T133	1		T166	2		T167	1
all_levels[62]	6	1			T168	1		T153	1		T169	2
all_levels[63]	4	1			T133	1		T170	1		T171	1
all_levels[64]	74	1			T14	1		T15	1		T16	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22902310

1

T5

18

T7

20

T10

5

auto[1]

3826

1

T2

1

T4

1

T21

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[34]]	[auto[1]]	0	1	1
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	22735599	1			T5	11		T7	17		T10	5
all_levels[0]	auto[1]	3375	1			T2	1		T4	1		T21	1
all_levels[1]	auto[0]	159951	1			T7	1		T11	1		T13	1
all_levels[1]	auto[1]	112	1			T94	1		T24	32		T172	1
all_levels[2]	auto[0]	2084	1			T12	1		T93	2		T94	1
all_levels[2]	auto[1]	31	1			T135	1		T120	2		T173	1
all_levels[3]	auto[0]	846	1			T13	2		T93	2		T33	3
all_levels[3]	auto[1]	31	1			T174	1		T175	2		T176	1
all_levels[4]	auto[0]	526	1			T7	1		T93	1		T94	1
all_levels[4]	auto[1]	13	1			T177	1		T175	1		T178	1
all_levels[5]	auto[0]	436	1			T13	2		T93	1		T33	1
all_levels[5]	auto[1]	14	1			T179	3		T180	1		T181	2
all_levels[6]	auto[0]	329	1			T5	2		T33	7		T114	2
all_levels[6]	auto[1]	21	1			T157	2		T182	1		T183	2
all_levels[7]	auto[0]	246	1			T115	2		T48	1		T14	2
all_levels[7]	auto[1]	12	1			T184	1		T185	1		T186	3
all_levels[8]	auto[0]	209	1			T13	4		T94	2		T33	4
all_levels[8]	auto[1]	11	1			T120	1		T187	1		T188	1
all_levels[9]	auto[0]	169	1			T5	1		T11	1		T13	1
all_levels[9]	auto[1]	10	1			T189	1		T190	2		T191	1
all_levels[10]	auto[0]	167	1			T11	1		T13	1		T93	1
all_levels[10]	auto[1]	10	1			T144	1		T192	1		T193	1
all_levels[11]	auto[0]	137	1			T13	2		T33	1		T16	1
all_levels[11]	auto[1]	16	1			T194	1		T195	2		T196	2
all_levels[12]	auto[0]	117	1			T5	2		T13	2		T33	2
all_levels[12]	auto[1]	5	1			T197	1		T198	1		T178	2
all_levels[13]	auto[0]	119	1			T7	1		T94	1		T116	1
all_levels[13]	auto[1]	10	1			T199	1		T200	1		T149	1
all_levels[14]	auto[0]	100	1			T94	1		T115	1		T117	1
all_levels[14]	auto[1]	7	1			T201	1		T202	2		T203	1
all_levels[15]	auto[0]	86	1			T115	1		T14	1		T118	1
all_levels[15]	auto[1]	7	1			T204	1		T205	1		T206	2
all_levels[16]	auto[0]	68	1			T116	1		T119	1		T120	1
all_levels[16]	auto[1]	4	1			T207	1		T208	1		T209	1
all_levels[17]	auto[0]	81	1			T14	1		T15	1		T121	1
all_levels[17]	auto[1]	7	1			T210	1		T195	1		T211	1
all_levels[18]	auto[0]	75	1			T49	1		T118	1		T122	1
all_levels[18]	auto[1]	6	1			T144	1		T212	1		T213	1
all_levels[19]	auto[0]	56	1			T122	1		T98	1		T121	1
all_levels[19]	auto[1]	1	1			T214	1		-	-		-	-
all_levels[20]	auto[0]	53	1			T115	1		T123	1		T121	2
all_levels[20]	auto[1]	5	1			T213	1		T215	1		T216	3
all_levels[21]	auto[0]	40	1			T118	1		T98	1		T124	1
all_levels[21]	auto[1]	5	1			T217	2		T218	2		T219	1
all_levels[22]	auto[0]	41	1			T15	1		T98	1		T117	1
all_levels[22]	auto[1]	7	1			T220	2		T221	1		T175	1
all_levels[23]	auto[0]	49	1			T49	1		T125	1		T116	2
all_levels[23]	auto[1]	8	1			T222	1		T223	1		T224	1
all_levels[24]	auto[0]	46	1			T115	1		T121	1		T106	1
all_levels[24]	auto[1]	3	1			T120	1		T225	1		T226	1
all_levels[25]	auto[0]	43	1			T121	1		T106	1		T117	1
all_levels[25]	auto[1]	9	1			T199	1		T227	3		T212	2
all_levels[26]	auto[0]	51	1			T13	1		T115	1		T126	1
all_levels[26]	auto[1]	7	1			T228	1		T153	1		T229	2
all_levels[27]	auto[0]	38	1			T115	1		T127	1		T128	1
all_levels[27]	auto[1]	8	1			T230	2		T231	1		T232	1
all_levels[28]	auto[0]	36	1			T119	1		T124	1		T129	1
all_levels[28]	auto[1]	3	1			T233	1		T234	2		-	-
all_levels[29]	auto[0]	24	1			T130	1		T131	1		T132	1
all_levels[29]	auto[1]	3	1			T130	1		T223	1		T154	1
all_levels[30]	auto[0]	34	1			T102	2		T133	1		T134	1
all_levels[30]	auto[1]	1	1			T134	1		-	-		-	-
all_levels[31]	auto[0]	28	1			T5	1		T135	1		T15	1
all_levels[31]	auto[1]	4	1			T135	4		-	-		-	-
all_levels[32]	auto[0]	23	1			T12	1		T127	1		T129	1
all_levels[32]	auto[1]	4	1			T129	1		T235	1		T236	1
all_levels[33]	auto[0]	23	1			T98	1		T103	1		T96	2
all_levels[33]	auto[1]	5	1			T160	2		T237	1		T238	2
all_levels[34]	auto[0]	23	1			T12	1		T16	1		T119	1
all_levels[35]	auto[0]	18	1			T49	1		T136	2		T137	1
all_levels[35]	auto[1]	4	1			T239	1		T240	1		T154	1
all_levels[36]	auto[0]	28	1			T15	1		T138	2		T139	1
all_levels[36]	auto[1]	4	1			T197	2		T241	1		T242	1
all_levels[37]	auto[0]	15	1			T14	1		T106	1		T100	1
all_levels[38]	auto[0]	16	1			T5	1		T116	1		T98	1
all_levels[38]	auto[1]	5	1			T243	2		T244	1		T245	1
all_levels[39]	auto[0]	19	1			T16	1		T116	1		T98	1
all_levels[39]	auto[1]	2	1			T246	1		T247	1		-	-
all_levels[40]	auto[0]	8	1			T16	1		T140	1		T141	1
all_levels[40]	auto[1]	2	1			T248	2		-	-		-	-
all_levels[41]	auto[0]	15	1			T142	1		T143	1		T136	1
all_levels[41]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[42]	auto[0]	19	1			T106	3		T144	1		T136	1
all_levels[42]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[43]	auto[0]	9	1			T106	1		T103	1		T145	1
all_levels[44]	auto[0]	8	1			T146	1		T103	1		T147	1
all_levels[44]	auto[1]	1	1			T251	1		-	-		-	-
all_levels[45]	auto[0]	12	1			T148	1		T96	1		T149	1
all_levels[46]	auto[0]	12	1			T119	1		T148	2		T150	1
all_levels[46]	auto[1]	3	1			T189	1		T252	1		T204	1
all_levels[47]	auto[0]	12	1			T124	1		T107	1		T151	1
all_levels[47]	auto[1]	1	1			T160	1		-	-		-	-
all_levels[48]	auto[0]	3	1			T152	1		T153	1		T154	1
all_levels[49]	auto[0]	8	1			T126	1		T155	1		T156	1
all_levels[50]	auto[0]	5	1			T155	1		T157	1		T96	1
all_levels[50]	auto[1]	3	1			T200	3		-	-		-	-
all_levels[51]	auto[0]	8	1			T118	1		T136	1		T156	1
all_levels[51]	auto[1]	1	1			T253	1		-	-		-	-
all_levels[52]	auto[0]	9	1			T13	1		T158	1		T132	1
all_levels[52]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[53]	auto[0]	3	1			T155	1		T96	1		T159	1
all_levels[54]	auto[0]	7	1			T15	1		T128	1		T160	1
all_levels[54]	auto[1]	3	1			T255	1		T256	1		T257	1
all_levels[55]	auto[0]	10	1			T125	1		T161	2		T140	1
all_levels[55]	auto[1]	1	1			T258	1		-	-		-	-
all_levels[56]	auto[0]	6	1			T140	1		T150	1		T162	1
all_levels[56]	auto[1]	3	1			T181	2		T259	1		-	-
all_levels[57]	auto[0]	5	1			T107	1		T149	1		T163	1
all_levels[57]	auto[1]	1	1			T260	1		-	-		-	-
all_levels[58]	auto[0]	7	1			T13	1		T156	1		T164	1
all_levels[58]	auto[1]	1	1			T261	1		-	-		-	-
all_levels[59]	auto[0]	6	1			T117	1		T138	1		T165	1
all_levels[59]	auto[1]	1	1			T262	1		-	-		-	-
all_levels[60]	auto[0]	8	1			T138	1		T147	1		T160	1
all_levels[60]	auto[1]	2	1			T212	1		T195	1		-	-
all_levels[61]	auto[0]	7	1			T133	1		T166	2		T167	1
all_levels[62]	auto[0]	5	1			T168	1		T153	1		T169	2
all_levels[62]	auto[1]	1	1			T263	1		-	-		-	-
all_levels[63]	auto[0]	4	1			T133	1		T170	1		T171	1
all_levels[64]	auto[0]	65	1			T14	1		T15	1		T16	1
all_levels[64]	auto[1]	9	1			T197	2		T213	1		T264	1