Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	79196	1			T1	2		T2	1		T3	2
all_pins[1]	79196	1			T1	2		T2	1		T3	2
all_pins[2]	79196	1			T1	2		T2	1		T3	2
all_pins[3]	79196	1			T1	2		T2	1		T3	2
all_pins[4]	79196	1			T1	2		T2	1		T3	2
all_pins[5]	79196	1			T1	2		T2	1		T3	2
all_pins[6]	79196	1			T1	2		T2	1		T3	2
all_pins[7]	79196	1			T1	2		T2	1		T3	2
all_pins[8]	79196	1			T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	676146	1			T1	18		T2	8		T3	18
values[0x1]	36618	1			T2	1		T4	1		T5	4
transitions[0x0=>0x1]	29713	1			T2	1		T4	1		T5	4
transitions[0x1=>0x0]	29459	1			T5	3		T7	11		T10	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	62319	1			T1	2		T3	2		T5	2
all_pins[0]	values[0x1]	16877	1			T2	1		T4	1		T5	3
all_pins[0]	transitions[0x0=>0x1]	16425	1			T2	1		T4	1		T5	3
all_pins[0]	transitions[0x1=>0x0]	755	1			T10	1		T16	6		T43	3
all_pins[1]	values[0x0]	77989	1			T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	1207	1			T10	1		T97	3		T16	8
all_pins[1]	transitions[0x0=>0x1]	1109	1			T97	3		T16	8		T19	6
all_pins[1]	transitions[0x1=>0x0]	1891	1			T7	3		T10	2		T11	2
all_pins[2]	values[0x0]	77207	1			T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	1989	1			T7	3		T10	3		T11	2
all_pins[2]	transitions[0x0=>0x1]	1922	1			T7	3		T11	2		T12	2
all_pins[2]	transitions[0x1=>0x0]	189	1			T14	2		T125	1		T20	1
all_pins[3]	values[0x0]	78940	1			T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	256	1			T10	3		T14	2		T125	1
all_pins[3]	transitions[0x0=>0x1]	216	1			T14	2		T125	1		T20	1
all_pins[3]	transitions[0x1=>0x0]	275	1			T10	1		T19	17		T20	9
all_pins[4]	values[0x0]	78881	1			T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	315	1			T10	4		T19	17		T20	9
all_pins[4]	transitions[0x0=>0x1]	251	1			T19	14		T20	7		T43	3
all_pins[4]	transitions[0x1=>0x0]	121	1			T20	1		T43	4		T99	1
all_pins[5]	values[0x0]	79011	1			T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	185	1			T10	4		T19	3		T20	3
all_pins[5]	transitions[0x0=>0x1]	146	1			T10	2		T19	3		T20	3
all_pins[5]	transitions[0x1=>0x0]	734	1			T5	1		T7	2		T13	4
all_pins[6]	values[0x0]	78423	1			T1	2		T2	1		T3	2
all_pins[6]	values[0x1]	773	1			T5	1		T7	2		T10	2
all_pins[6]	transitions[0x0=>0x1]	722	1			T5	1		T7	2		T10	1
all_pins[6]	transitions[0x1=>0x0]	306	1			T30	1		T43	2		T106	2
all_pins[7]	values[0x0]	78839	1			T1	2		T2	1		T3	2
all_pins[7]	values[0x1]	357	1			T10	1		T30	1		T43	4
all_pins[7]	transitions[0x0=>0x1]	195	1			T30	1		T43	4		T106	1
all_pins[7]	transitions[0x1=>0x0]	14497	1			T11	3		T13	10		T27	5
all_pins[8]	values[0x0]	64537	1			T1	2		T2	1		T3	2
all_pins[8]	values[0x1]	14659	1			T10	1		T11	3		T13	10
all_pins[8]	transitions[0x0=>0x1]	8727	1			T11	1		T13	1		T27	1
all_pins[8]	transitions[0x1=>0x0]	10691	1			T5	2		T7	6		T13	3