Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7099065	1			T5	4		T7	12		T10	5
all_levels[1]	1047098	1			T7	5		T13	4		T31	2
all_levels[2]	514526	1			T13	3		T27	4		T93	13
all_levels[3]	350660	1			T5	3		T13	5		T93	5
all_levels[4]	305817	1			T5	1		T93	2		T114	56
all_levels[5]	195833	1			T93	2		T94	2		T33	1
all_levels[6]	210811	1			T33	1		T114	1		T47	8
all_levels[7]	194833	1			T93	1		T94	2		T47	7
all_levels[8]	166781	1			T7	1		T114	4		T47	8
all_levels[9]	201384	1			T5	5		T12	2		T33	1
all_levels[10]	150721	1			T33	4		T114	1		T115	1
all_levels[11]	289549	1			T12	1		T114	76		T135	6
all_levels[12]	506255	1			T93	96		T33	2		T115	11
all_levels[13]	177505	1			T33	2		T115	1		T30	37
all_levels[14]	156315	1			T5	3		T7	2		T114	3
all_levels[15]	596108	1			T33	15		T115	2		T47	10
all_levels[16]	140822	1			T94	2		T114	3		T115	2
all_levels[17]	253888	1			T11	1		T33	20		T114	1
all_levels[18]	127003	1			T94	3		T33	5		T47	10
all_levels[19]	210051	1			T93	1		T94	1		T115	3
all_levels[20]	134317	1			T33	11		T114	3		T115	2
all_levels[21]	204491	1			T12	8		T33	57		T114	44
all_levels[22]	118993	1			T93	11		T33	1		T114	2
all_levels[23]	229612	1			T93	1		T94	2		T114	1
all_levels[24]	171209	1			T93	7		T33	5		T114	35
all_levels[25]	120154	1			T33	4		T114	3		T115	1
all_levels[26]	185273	1			T114	4		T47	8		T97	1
all_levels[27]	242780	1			T33	4		T47	5		T276	1
all_levels[28]	154262	1			T11	1		T93	1		T114	2
all_levels[29]	120468	1			T93	3		T94	2		T33	2
all_levels[30]	104214	1			T93	1		T33	2		T30	3
all_levels[31]	628064	1			T93	1		T33	1		T135	5
all_levels[32]	7597099	1			T5	3		T11	12		T12	11

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22902310

1

T5

18

T7

20

T10

5

auto[1]

3651

1

T5

1

T11

1

T13

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7097007	1			T5	4		T7	12		T10	5
all_levels[0]	auto[1]	2058	1			T11	1		T94	3		T391	9
all_levels[1]	auto[0]	1046799	1			T7	5		T13	3		T31	2
all_levels[1]	auto[1]	299	1			T13	1		T94	4		T364	6
all_levels[2]	auto[0]	514492	1			T13	3		T27	4		T93	13
all_levels[2]	auto[1]	34	1			T150	2		T151	1		T406	2
all_levels[3]	auto[0]	350600	1			T5	3		T13	5		T93	5
all_levels[3]	auto[1]	60	1			T16	4		T302	2		T106	4
all_levels[4]	auto[0]	305792	1			T5	1		T93	2		T114	56
all_levels[4]	auto[1]	25	1			T265	4		T134	1		T107	1
all_levels[5]	auto[0]	195810	1			T93	2		T94	1		T33	1
all_levels[5]	auto[1]	23	1			T94	1		T124	1		T307	1
all_levels[6]	auto[0]	210787	1			T33	1		T114	1		T47	8
all_levels[6]	auto[1]	24	1			T407	1		T230	1		T178	2
all_levels[7]	auto[0]	194699	1			T93	1		T94	2		T47	7
all_levels[7]	auto[1]	134	1			T279	5		T74	3		T143	6
all_levels[8]	auto[0]	166759	1			T7	1		T114	4		T47	8
all_levels[8]	auto[1]	22	1			T393	1		T309	1		T173	2
all_levels[9]	auto[0]	201367	1			T5	5		T12	2		T33	1
all_levels[9]	auto[1]	17	1			T408	1		T358	3		T409	1
all_levels[10]	auto[0]	150699	1			T33	4		T114	1		T115	1
all_levels[10]	auto[1]	22	1			T337	1		T410	1		T202	1
all_levels[11]	auto[0]	289526	1			T12	1		T114	76		T135	2
all_levels[11]	auto[1]	23	1			T135	4		T411	1		T177	2
all_levels[12]	auto[0]	506222	1			T93	96		T33	2		T115	11
all_levels[12]	auto[1]	33	1			T302	3		T173	1		T412	1
all_levels[13]	auto[0]	177477	1			T33	2		T115	1		T30	37
all_levels[13]	auto[1]	28	1			T101	1		T172	1		T299	10
all_levels[14]	auto[0]	156294	1			T5	3		T7	2		T114	3
all_levels[14]	auto[1]	21	1			T413	1		T414	1		T415	1
all_levels[15]	auto[0]	596037	1			T33	15		T115	2		T47	10
all_levels[15]	auto[1]	71	1			T105	17		T282	1		T340	2
all_levels[16]	auto[0]	140814	1			T94	1		T114	3		T115	2
all_levels[16]	auto[1]	8	1			T94	1		T75	1		T397	1
all_levels[17]	auto[0]	253868	1			T11	1		T33	20		T114	1
all_levels[17]	auto[1]	20	1			T172	1		T416	1		T417	1
all_levels[18]	auto[0]	126985	1			T94	2		T33	5		T47	10
all_levels[18]	auto[1]	18	1			T94	1		T418	1		T419	2
all_levels[19]	auto[0]	210035	1			T93	1		T94	1		T115	3
all_levels[19]	auto[1]	16	1			T134	3		T420	1		T421	1
all_levels[20]	auto[0]	134288	1			T33	11		T114	3		T115	2
all_levels[20]	auto[1]	29	1			T422	1		T423	1		T96	1
all_levels[21]	auto[0]	204473	1			T12	8		T33	56		T114	44
all_levels[21]	auto[1]	18	1			T33	1		T16	1		T144	1
all_levels[22]	auto[0]	118983	1			T93	11		T33	1		T114	2
all_levels[22]	auto[1]	10	1			T212	1		T424	1		T419	1
all_levels[23]	auto[0]	229597	1			T93	1		T94	2		T114	1
all_levels[23]	auto[1]	15	1			T205	1		T425	2		T426	2
all_levels[24]	auto[0]	171197	1			T93	7		T33	5		T114	35
all_levels[24]	auto[1]	12	1			T16	1		T362	1		T427	1
all_levels[25]	auto[0]	120136	1			T33	4		T114	3		T115	1
all_levels[25]	auto[1]	18	1			T106	1		T129	1		T150	3
all_levels[26]	auto[0]	185251	1			T114	4		T47	8		T97	1
all_levels[26]	auto[1]	22	1			T341	3		T202	1		T428	1
all_levels[27]	auto[0]	242762	1			T33	4		T47	5		T276	1
all_levels[27]	auto[1]	18	1			T144	1		T155	1		T202	2
all_levels[28]	auto[0]	154250	1			T11	1		T93	1		T114	2
all_levels[28]	auto[1]	12	1			T125	1		T144	1		T429	1
all_levels[29]	auto[0]	120453	1			T93	3		T94	2		T33	2
all_levels[29]	auto[1]	15	1			T294	1		T342	2		T271	1
all_levels[30]	auto[0]	104203	1			T93	1		T33	2		T30	3
all_levels[30]	auto[1]	11	1			T155	1		T430	1		T431	1
all_levels[31]	auto[0]	628047	1			T93	1		T33	1		T135	1
all_levels[31]	auto[1]	17	1			T135	4		T432	1		T433	1
all_levels[32]	auto[0]	7596601	1			T5	2		T11	12		T12	10
all_levels[32]	auto[1]	498	1			T5	1		T12	1		T115	1