Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	676	1			T10	4		T43	14		T72	4
all_values[1]	676	1			T10	4		T43	14		T72	4
all_values[2]	676	1			T10	4		T43	14		T72	4
all_values[3]	676	1			T10	4		T43	14		T72	4
all_values[4]	676	1			T10	4		T43	14		T72	4
all_values[5]	676	1			T10	4		T43	14		T72	4
all_values[6]	676	1			T10	4		T43	14		T72	4
all_values[7]	676	1			T10	4		T43	14		T72	4
all_values[8]	676	1			T10	4		T43	14		T72	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3257

1

T10

14

T43

72

T72

21

auto[1]

2827

1

T10

22

T43

54

T72

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1965

1

T10

4

T43

34

T72

16

auto[1]

4119

1

T10

32

T43

92

T72

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3522

1

T10

16

T43

71

T72

22

auto[1]

2562

1

T10

20

T43

55

T72

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	216	1			T10	1		T43	7		T72	2
all_values[0]	auto[0]	auto[1]	auto[1]	164	1			T43	2		T73	1		T87	2
all_values[0]	auto[1]	auto[0]	auto[1]	175	1			T10	2		T43	3		T72	1
all_values[0]	auto[1]	auto[1]	auto[1]	121	1			T10	1		T43	2		T72	1
all_values[1]	auto[0]	auto[0]	auto[0]	202	1			T10	1		T43	2		T72	3
all_values[1]	auto[0]	auto[1]	auto[0]	188	1			T10	2		T43	4		T72	1
all_values[1]	auto[1]	auto[0]	auto[1]	146	1			T43	4		T73	3		T87	2
all_values[1]	auto[1]	auto[1]	auto[1]	140	1			T10	1		T43	4		T87	1
all_values[2]	auto[0]	auto[0]	auto[0]	142	1			T72	2		T73	1		T87	1
all_values[2]	auto[0]	auto[0]	auto[1]	61	1			T43	2		T73	3		T87	1
all_values[2]	auto[0]	auto[1]	auto[0]	105	1			T43	4		T72	2		T87	3
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T10	1		T88	2		T110	2
all_values[2]	auto[1]	auto[0]	auto[1]	160	1			T10	1		T43	4		T73	3
all_values[2]	auto[1]	auto[1]	auto[1]	139	1			T10	2		T43	4		T87	1
all_values[3]	auto[0]	auto[0]	auto[0]	132	1			T10	1		T43	1		T72	1
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T43	2		T73	1		T87	1
all_values[3]	auto[0]	auto[1]	auto[0]	124	1			T72	1		T87	1		T107	3
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T10	2		T43	3		T73	2
all_values[3]	auto[1]	auto[0]	auto[1]	155	1			T43	3		T73	3		T87	2
all_values[3]	auto[1]	auto[1]	auto[1]	128	1			T10	1		T43	5		T72	2
all_values[4]	auto[0]	auto[0]	auto[0]	140	1			T43	5		T87	3		T107	1
all_values[4]	auto[0]	auto[0]	auto[1]	65	1			T43	2		T72	1		T107	1
all_values[4]	auto[0]	auto[1]	auto[0]	127	1			T43	2		T72	2		T73	1
all_values[4]	auto[0]	auto[1]	auto[1]	65	1			T10	2		T43	2		T73	1
all_values[4]	auto[1]	auto[0]	auto[1]	159	1			T43	1		T72	1		T73	1
all_values[4]	auto[1]	auto[1]	auto[1]	120	1			T10	2		T43	2		T73	4
all_values[5]	auto[0]	auto[0]	auto[0]	152	1			T43	4		T72	1		T73	2
all_values[5]	auto[0]	auto[0]	auto[1]	62	1			T43	1		T73	1		T107	2
all_values[5]	auto[0]	auto[1]	auto[0]	117	1			T73	1		T87	2		T111	1
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T10	1		T43	2		T72	1
all_values[5]	auto[1]	auto[0]	auto[1]	130	1			T43	4		T72	1		T73	1
all_values[5]	auto[1]	auto[1]	auto[1]	145	1			T10	3		T43	3		T72	1
all_values[6]	auto[0]	auto[0]	auto[0]	161	1			T43	4		T72	1		T73	3
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T10	2		T43	1		T72	1
all_values[6]	auto[0]	auto[1]	auto[0]	118	1			T73	2		T107	1		T110	2
all_values[6]	auto[0]	auto[1]	auto[1]	63	1			T43	2		T87	2		T111	2
all_values[6]	auto[1]	auto[0]	auto[1]	150	1			T43	5		T72	1		T73	1
all_values[6]	auto[1]	auto[1]	auto[1]	115	1			T10	2		T43	2		T72	1
all_values[7]	auto[0]	auto[0]	auto[0]	147	1			T43	6		T72	2		T73	3
all_values[7]	auto[0]	auto[0]	auto[1]	60	1			T10	1		T73	1		T111	1
all_values[7]	auto[0]	auto[1]	auto[0]	110	1			T43	2		T87	1		T88	1
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T43	3		T107	1		T88	1
all_values[7]	auto[1]	auto[0]	auto[1]	152	1			T10	2		T43	1		T72	2
all_values[7]	auto[1]	auto[1]	auto[1]	132	1			T10	1		T43	2		T73	1
all_values[8]	auto[0]	auto[0]	auto[1]	194	1			T10	2		T43	5		T73	2
all_values[8]	auto[0]	auto[1]	auto[1]	187	1			T43	3		T72	1		T73	1
all_values[8]	auto[1]	auto[0]	auto[1]	162	1			T10	1		T43	5		T72	1
all_values[8]	auto[1]	auto[1]	auto[1]	133	1			T10	1		T43	1		T72	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal