Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	76011	1			T1	1		T3	1		T5	2
all_values[1]	76011	1			T1	1		T3	1		T5	2
all_values[2]	76011	1			T1	1		T3	1		T5	2
all_values[3]	76011	1			T1	1		T3	1		T5	2
all_values[4]	76011	1			T1	1		T3	1		T5	2
all_values[5]	76011	1			T1	1		T3	1		T5	2
all_values[6]	76011	1			T1	1		T3	1		T5	2
all_values[7]	76011	1			T1	1		T3	1		T5	2
all_values[8]	76011	1			T1	1		T3	1		T5	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

349130

1

T1

5

T3

8

T5

18

auto[1]

334969

1

T1

4

T3

1

T6

378

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620441

1

T1

7

T3

7

T5

13

auto[1]

63658

1

T1

2

T3

2

T5

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24449	1			T8	11		T11	8		T12	4
all_values[0]	auto[0]	auto[1]	15794	1			T1	1		T3	1		T5	2
all_values[0]	auto[1]	auto[0]	20958	1			T6	1		T12	9		T15	9
all_values[0]	auto[1]	auto[1]	14810	1			T6	68		T11	4		T12	2
all_values[1]	auto[0]	auto[0]	42247	1			T3	1		T5	2		T6	30
all_values[1]	auto[0]	auto[1]	1511	1			T8	5		T41	5		T42	10
all_values[1]	auto[1]	auto[0]	30765	1			T1	1		T6	39		T8	16
all_values[1]	auto[1]	auto[1]	1488	1			T6	14		T8	27		T12	4
all_values[2]	auto[0]	auto[0]	36342	1			T1	1		T5	1		T6	44
all_values[2]	auto[0]	auto[1]	2129	1			T5	1		T7	1		T11	5
all_values[2]	auto[1]	auto[0]	35516	1			T3	1		T6	39		T8	43
all_values[2]	auto[1]	auto[1]	2024	1			T11	3		T14	1		T19	4
all_values[3]	auto[0]	auto[0]	37009	1			T1	1		T3	1		T5	2
all_values[3]	auto[0]	auto[1]	226	1			T6	1		T15	2		T70	5
all_values[3]	auto[1]	auto[0]	38550	1			T6	44		T8	75		T11	12
all_values[3]	auto[1]	auto[1]	226	1			T17	2		T18	1		T70	2
all_values[4]	auto[0]	auto[0]	34593	1			T3	1		T5	2		T7	2
all_values[4]	auto[0]	auto[1]	312	1			T18	3		T70	6		T27	1
all_values[4]	auto[1]	auto[0]	40673	1			T1	1		T6	73		T8	67
all_values[4]	auto[1]	auto[1]	433	1			T6	10		T8	8		T70	3
all_values[5]	auto[0]	auto[0]	37131	1			T3	1		T5	2		T6	53
all_values[5]	auto[0]	auto[1]	160	1			T18	4		T70	4		T27	4
all_values[5]	auto[1]	auto[0]	38566	1			T1	1		T6	30		T8	90
all_values[5]	auto[1]	auto[1]	154	1			T18	2		T70	2		T107	1
all_values[6]	auto[0]	auto[0]	38716	1			T1	1		T3	1		T5	2
all_values[6]	auto[0]	auto[1]	154	1			T18	2		T32	3		T34	1
all_values[6]	auto[1]	auto[0]	37004	1			T8	75		T11	18		T12	2
all_values[6]	auto[1]	auto[1]	137	1			T18	1		T70	4		T27	4
all_values[7]	auto[0]	auto[0]	38917	1			T3	1		T5	2		T6	34
all_values[7]	auto[0]	auto[1]	290	1			T6	5		T8	5		T18	4
all_values[7]	auto[1]	auto[0]	36459	1			T1	1		T6	44		T8	15
all_values[7]	auto[1]	auto[1]	345	1			T15	6		T18	3		T70	3
all_values[8]	auto[0]	auto[0]	27679	1			T6	4		T8	17		T11	6
all_values[8]	auto[0]	auto[1]	11471	1			T1	1		T3	1		T5	2
all_values[8]	auto[1]	auto[0]	24867	1			T11	4		T71	1		T17	7
all_values[8]	auto[1]	auto[1]	11994	1			T6	16		T8	15		T11	16