Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2585

1

T1

1

T2

21

T3

1

auto[UartRx]

2585

1

T1

1

T2

21

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4511	1			T1	2		T2	42		T3	2
values[1]	43	1			T27	1		T33	1		T36	1
values[2]	49	1			T26	3		T27	1		T31	1
values[3]	74	1			T30	1		T31	1		T33	4
values[4]	51	1			T18	2		T27	2		T31	2
values[5]	61	1			T32	1		T107	1		T324	1
values[6]	63	1			T26	2		T31	1		T32	1
values[7]	58	1			T30	1		T33	1		T35	2
values[8]	61	1			T18	3		T31	3		T32	2
values[9]	74	1			T18	1		T30	1		T31	2
values[10]	81	1			T26	1		T30	1		T31	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2348	1			T1	1		T2	21		T3	1
auto[UartTx]	values[1]	11	1			T324	1		T389	1		T390	1
auto[UartTx]	values[2]	18	1			T26	2		T27	1		T31	1
auto[UartTx]	values[3]	29	1			T30	1		T33	2		T391	1
auto[UartTx]	values[4]	20	1			T18	1		T27	1		T31	1
auto[UartTx]	values[5]	23	1			T107	1		T106	2		T392	1
auto[UartTx]	values[6]	24	1			T26	1		T31	1		T32	1
auto[UartTx]	values[7]	29	1			T35	1		T87	1		T88	2
auto[UartTx]	values[8]	18	1			T18	1		T31	1		T34	1
auto[UartTx]	values[9]	28	1			T18	1		T31	2		T34	1
auto[UartTx]	values[10]	28	1			T32	2		T34	1		T87	1
auto[UartRx]	values[0]	2163	1			T1	1		T2	21		T3	1
auto[UartRx]	values[1]	32	1			T27	1		T33	1		T36	1
auto[UartRx]	values[2]	31	1			T26	1		T33	1		T107	1
auto[UartRx]	values[3]	45	1			T31	1		T33	2		T391	1
auto[UartRx]	values[4]	31	1			T18	1		T27	1		T31	1
auto[UartRx]	values[5]	38	1			T32	1		T324	1		T106	4
auto[UartRx]	values[6]	39	1			T26	1		T33	1		T35	1
auto[UartRx]	values[7]	29	1			T30	1		T33	1		T35	1
auto[UartRx]	values[8]	43	1			T18	2		T31	2		T32	2
auto[UartRx]	values[9]	46	1			T30	1		T32	3		T34	1
auto[UartRx]	values[10]	53	1			T26	1		T30	1		T31	2