Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1868	1			T1	5		T3	2		T11	5
auto[BaudRate115200]	1542	1			T6	1		T7	1		T8	1
auto[BaudRate230400]	1472	1			T6	1		T8	2		T11	2
auto[BaudRate128Kbps]	1487	1			T6	2		T11	1		T12	2
auto[BaudRate256Kbps]	1690	1			T7	1		T11	5		T12	1
auto[BaudRate1Mbps]	1270	1			T5	2		T14	1		T69	1
auto[BaudRate1p5Mbps]	1035	1			T23	3		T393	15		T18	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	779	1			T1	5		T308	2		T47	5
freqs[25]	978	1			T16	2		T46	6		T30	18
freqs[48]	409	1			T84	1		T264	2		T34	18
freqs[50]	643	1			T14	1		T31	12		T336	2
freqs[100]	940	1			T24	9		T26	10		T45	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	108	1			T1	5		T394	3		T310	2
auto[BaudRate9600]	freqs[25]	188	1			T16	1		T46	1		T30	4
auto[BaudRate9600]	freqs[48]	96	1			T84	1		T264	1		T34	2
auto[BaudRate9600]	freqs[50]	153	1			T31	4		T336	2		T249	13
auto[BaudRate9600]	freqs[100]	179	1			T26	1		T45	1		T395	7
auto[BaudRate115200]	freqs[24]	106	1			T308	1		T394	9		T396	3
auto[BaudRate115200]	freqs[25]	149	1			T16	1		T30	4		T304	1
auto[BaudRate115200]	freqs[48]	40	1			T261	2		T397	1		T398	2
auto[BaudRate115200]	freqs[50]	68	1			T31	2		T249	4		T399	6
auto[BaudRate115200]	freqs[100]	141	1			T24	3		T26	2		T45	1
auto[BaudRate230400]	freqs[24]	105	1			T308	1		T394	3		T310	1
auto[BaudRate230400]	freqs[25]	115	1			T400	6		T288	1		T125	14
auto[BaudRate230400]	freqs[48]	47	1			T34	2		T261	2		T309	1
auto[BaudRate230400]	freqs[50]	90	1			T31	2		T401	6		T249	10
auto[BaudRate230400]	freqs[100]	116	1			T24	3		T26	2		T292	1
auto[BaudRate128Kbps]	freqs[24]	107	1			T47	1		T394	3		T280	2
auto[BaudRate128Kbps]	freqs[25]	104	1			T46	1		T30	2		T304	1
auto[BaudRate128Kbps]	freqs[48]	54	1			T34	4		T261	3		T332	1
auto[BaudRate128Kbps]	freqs[50]	79	1			T276	2		T401	6		T249	8
auto[BaudRate128Kbps]	freqs[100]	115	1			T24	3		T26	1		T45	1
auto[BaudRate256Kbps]	freqs[24]	158	1			T47	1		T394	9		T280	3
auto[BaudRate256Kbps]	freqs[25]	196	1			T46	2		T30	3		T277	1
auto[BaudRate256Kbps]	freqs[48]	52	1			T34	6		T261	1		T358	1
auto[BaudRate256Kbps]	freqs[50]	98	1			T31	1		T375	1		T401	6
auto[BaudRate256Kbps]	freqs[100]	137	1			T45	2		T115	1		T359	3
auto[BaudRate1Mbps]	freqs[24]	127	1			T47	3		T394	3		T357	1
auto[BaudRate1Mbps]	freqs[25]	138	1			T46	2		T30	5		T400	3
auto[BaudRate1Mbps]	freqs[48]	64	1			T264	1		T34	1		T309	2
auto[BaudRate1Mbps]	freqs[50]	83	1			T14	1		T276	2		T249	10
auto[BaudRate1Mbps]	freqs[100]	107	1			T26	3		T271	1		T359	1
auto[BaudRate1p5Mbps]	freqs[25]	88	1			T277	1		T400	6		T288	1
auto[BaudRate1p5Mbps]	freqs[48]	56	1			T34	3		T261	2		T299	1
auto[BaudRate1p5Mbps]	freqs[50]	72	1			T31	3		T276	1		T401	3
auto[BaudRate1p5Mbps]	freqs[100]	145	1			T26	1		T115	2		T271	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded