Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.45	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	7	123	94.62

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	7	123	94.62	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	21433081	1			T1	1		T3	1		T6	177
all_levels[1]	139622	1			T11	18		T19	3		T17	1
all_levels[2]	1866	1			T11	2		T19	1		T17	1
all_levels[3]	903	1			T11	1		T70	1		T112	4
all_levels[4]	616	1			T17	2		T112	4		T113	2
all_levels[5]	464	1			T17	2		T43	1		T96	1
all_levels[6]	357	1			T12	1		T17	1		T43	1
all_levels[7]	298	1			T15	1		T19	1		T70	1
all_levels[8]	228	1			T12	1		T43	1		T112	1
all_levels[9]	224	1			T11	1		T19	1		T41	1
all_levels[10]	168	1			T12	1		T112	1		T114	1
all_levels[11]	164	1			T19	2		T70	1		T114	1
all_levels[12]	150	1			T11	1		T12	1		T41	2
all_levels[13]	111	1			T17	1		T46	1		T115	1
all_levels[14]	89	1			T19	1		T41	1		T114	1
all_levels[15]	106	1			T15	2		T114	3		T116	1
all_levels[16]	109	1			T17	1		T117	2		T112	1
all_levels[17]	76	1			T117	1		T48	1		T116	2
all_levels[18]	81	1			T12	1		T19	1		T70	1
all_levels[19]	72	1			T41	1		T115	1		T97	1
all_levels[20]	65	1			T41	1		T117	1		T112	2
all_levels[21]	65	1			T19	1		T112	1		T114	1
all_levels[22]	63	1			T17	1		T70	1		T112	1
all_levels[23]	57	1			T19	1		T39	1		T118	1
all_levels[24]	43	1			T12	1		T112	2		T119	1
all_levels[25]	37	1			T12	1		T71	1		T120	1
all_levels[26]	61	1			T19	1		T41	1		T96	1
all_levels[27]	47	1			T17	1		T41	2		T70	1
all_levels[28]	39	1			T116	1		T121	1		T122	1
all_levels[29]	27	1			T70	2		T123	1		T124	1
all_levels[30]	29	1			T117	1		T125	1		T100	1
all_levels[31]	18	1			T15	1		T41	1		T126	1
all_levels[32]	35	1			T127	1		T128	2		T101	1
all_levels[33]	25	1			T114	1		T129	1		T121	2
all_levels[34]	29	1			T17	1		T120	1		T121	1
all_levels[35]	22	1			T108	1		T130	1		T131	1
all_levels[36]	20	1			T12	1		T116	1		T132	1
all_levels[37]	22	1			T19	2		T112	1		T116	1
all_levels[38]	18	1			T112	1		T100	1		T133	1
all_levels[39]	16	1			T125	1		T121	3		T123	1
all_levels[40]	14	1			T134	1		T108	1		T123	1
all_levels[41]	23	1			T17	1		T121	1		T122	1
all_levels[42]	17	1			T96	1		T129	1		T135	1
all_levels[43]	13	1			T129	1		T125	1		T116	1
all_levels[44]	8	1			T96	1		T121	1		T136	1
all_levels[45]	13	1			T17	1		T126	2		T137	1
all_levels[46]	12	1			T117	1		T137	1		T138	3
all_levels[47]	12	1			T139	1		T140	1		T141	2
all_levels[48]	4	1			T142	2		T143	1		T144	1
all_levels[49]	7	1			T132	1		T145	1		T133	1
all_levels[50]	11	1			T146	1		T147	1		T148	1
all_levels[51]	6	1			T149	1		T150	1		T147	1
all_levels[52]	11	1			T117	1		T129	1		T116	2
all_levels[53]	6	1			T116	1		T151	1		T152	1
all_levels[54]	13	1			T100	1		T153	1		T154	1
all_levels[55]	7	1			T155	1		T156	2		T157	1
all_levels[56]	7	1			T15	1		T116	1		T158	1
all_levels[57]	5	1			T129	2		T159	1		T158	1
all_levels[58]	8	1			T116	1		T160	1		T95	1
all_levels[59]	1	1			T161	1		-	-		-	-
all_levels[60]	2	1			T162	1		T163	1		-	-
all_levels[61]	3	1			T160	1		T164	1		T165	1
all_levels[62]	4	1			T123	1		T166	1		T167	2
all_levels[63]	6	1			T17	1		T116	1		T154	2
all_levels[64]	73	1			T15	1		T17	1		T129	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21575717

1

T6

136

T8

2374

T11

145

auto[1]

4092

1

T1

1

T3

1

T6

41

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	7	123	94.62	7

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[55] , all_levels[56] , all_levels[57]]	[auto[1]]	--	--	3
[all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	3
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	21429420	1			T6	136		T8	2374		T11	122
all_levels[0]	auto[1]	3661	1			T1	1		T3	1		T6	41
all_levels[1]	auto[0]	139547	1			T11	18		T19	3		T17	1
all_levels[1]	auto[1]	75	1			T114	1		T134	1		T168	1
all_levels[2]	auto[0]	1841	1			T11	2		T19	1		T17	1
all_levels[2]	auto[1]	25	1			T169	2		T170	2		T131	2
all_levels[3]	auto[0]	883	1			T11	1		T70	1		T112	4
all_levels[3]	auto[1]	20	1			T114	1		T171	1		T172	1
all_levels[4]	auto[0]	607	1			T17	2		T112	4		T113	2
all_levels[4]	auto[1]	9	1			T171	1		T173	1		T174	1
all_levels[5]	auto[0]	443	1			T17	2		T43	1		T96	1
all_levels[5]	auto[1]	21	1			T175	1		T176	1		T144	2
all_levels[6]	auto[0]	337	1			T12	1		T17	1		T43	1
all_levels[6]	auto[1]	20	1			T177	1		T178	1		T179	2
all_levels[7]	auto[0]	281	1			T15	1		T19	1		T70	1
all_levels[7]	auto[1]	17	1			T180	1		T150	1		T181	1
all_levels[8]	auto[0]	216	1			T12	1		T43	1		T112	1
all_levels[8]	auto[1]	12	1			T101	1		T182	1		T150	1
all_levels[9]	auto[0]	215	1			T11	1		T19	1		T41	1
all_levels[9]	auto[1]	9	1			T131	1		T183	2		T184	1
all_levels[10]	auto[0]	153	1			T12	1		T112	1		T114	1
all_levels[10]	auto[1]	15	1			T95	1		T180	1		T185	1
all_levels[11]	auto[0]	151	1			T19	2		T70	1		T114	1
all_levels[11]	auto[1]	13	1			T95	3		T171	1		T186	1
all_levels[12]	auto[0]	141	1			T11	1		T12	1		T41	2
all_levels[12]	auto[1]	9	1			T187	2		T159	1		T152	1
all_levels[13]	auto[0]	108	1			T17	1		T46	1		T115	1
all_levels[13]	auto[1]	3	1			T188	2		T189	1		-	-
all_levels[14]	auto[0]	84	1			T19	1		T41	1		T114	1
all_levels[14]	auto[1]	5	1			T190	1		T191	1		T192	1
all_levels[15]	auto[0]	93	1			T15	2		T114	3		T116	1
all_levels[15]	auto[1]	13	1			T170	1		T171	3		T180	1
all_levels[16]	auto[0]	98	1			T17	1		T117	2		T112	1
all_levels[16]	auto[1]	11	1			T193	1		T194	1		T195	1
all_levels[17]	auto[0]	71	1			T117	1		T48	1		T116	2
all_levels[17]	auto[1]	5	1			T176	1		T196	1		T197	1
all_levels[18]	auto[0]	73	1			T12	1		T19	1		T70	1
all_levels[18]	auto[1]	8	1			T101	5		T198	1		T199	1
all_levels[19]	auto[0]	66	1			T41	1		T115	1		T97	1
all_levels[19]	auto[1]	6	1			T198	1		T173	1		T200	1
all_levels[20]	auto[0]	63	1			T41	1		T117	1		T112	2
all_levels[20]	auto[1]	2	1			T201	1		T202	1		-	-
all_levels[21]	auto[0]	62	1			T19	1		T112	1		T114	1
all_levels[21]	auto[1]	3	1			T152	1		T203	1		T204	1
all_levels[22]	auto[0]	54	1			T17	1		T70	1		T112	1
all_levels[22]	auto[1]	9	1			T201	2		T138	1		T205	1
all_levels[23]	auto[0]	49	1			T19	1		T39	1		T118	1
all_levels[23]	auto[1]	8	1			T206	2		T207	1		T208	2
all_levels[24]	auto[0]	39	1			T12	1		T112	2		T119	1
all_levels[24]	auto[1]	4	1			T209	1		T210	2		T211	1
all_levels[25]	auto[0]	36	1			T12	1		T71	1		T120	1
all_levels[25]	auto[1]	1	1			T212	1		-	-		-	-
all_levels[26]	auto[0]	54	1			T19	1		T41	1		T96	1
all_levels[26]	auto[1]	7	1			T213	1		T214	1		T215	1
all_levels[27]	auto[0]	39	1			T17	1		T41	2		T70	1
all_levels[27]	auto[1]	8	1			T216	1		T217	4		T218	2
all_levels[28]	auto[0]	34	1			T116	1		T121	1		T122	1
all_levels[28]	auto[1]	5	1			T208	5		-	-		-	-
all_levels[29]	auto[0]	26	1			T70	2		T123	1		T124	1
all_levels[29]	auto[1]	1	1			T95	1		-	-		-	-
all_levels[30]	auto[0]	27	1			T117	1		T125	1		T100	1
all_levels[30]	auto[1]	2	1			T219	1		T220	1		-	-
all_levels[31]	auto[0]	17	1			T15	1		T41	1		T126	1
all_levels[31]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[32]	auto[0]	26	1			T127	1		T128	1		T101	1
all_levels[32]	auto[1]	9	1			T128	1		T146	2		T222	3
all_levels[33]	auto[0]	21	1			T114	1		T129	1		T121	2
all_levels[33]	auto[1]	4	1			T144	1		T223	2		T202	1
all_levels[34]	auto[0]	22	1			T17	1		T120	1		T121	1
all_levels[34]	auto[1]	7	1			T224	3		T225	1		T226	3
all_levels[35]	auto[0]	18	1			T108	1		T130	1		T131	1
all_levels[35]	auto[1]	4	1			T227	1		T192	1		T228	1
all_levels[36]	auto[0]	17	1			T12	1		T116	1		T132	1
all_levels[36]	auto[1]	3	1			T185	1		T229	2		-	-
all_levels[37]	auto[0]	21	1			T19	2		T112	1		T116	1
all_levels[37]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[38]	auto[0]	14	1			T112	1		T100	1		T133	1
all_levels[38]	auto[1]	4	1			T231	4		-	-		-	-
all_levels[39]	auto[0]	14	1			T125	1		T121	1		T123	1
all_levels[39]	auto[1]	2	1			T121	2		-	-		-	-
all_levels[40]	auto[0]	12	1			T134	1		T108	1		T123	1
all_levels[40]	auto[1]	2	1			T190	2		-	-		-	-
all_levels[41]	auto[0]	21	1			T17	1		T121	1		T122	1
all_levels[41]	auto[1]	2	1			T232	1		T233	1		-	-
all_levels[42]	auto[0]	13	1			T96	1		T129	1		T135	1
all_levels[42]	auto[1]	4	1			T234	1		T235	1		T236	1
all_levels[43]	auto[0]	10	1			T129	1		T125	1		T116	1
all_levels[43]	auto[1]	3	1			T145	2		T213	1		-	-
all_levels[44]	auto[0]	7	1			T96	1		T121	1		T136	1
all_levels[44]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[45]	auto[0]	10	1			T17	1		T126	1		T137	1
all_levels[45]	auto[1]	3	1			T126	1		T237	2		-	-
all_levels[46]	auto[0]	9	1			T117	1		T137	1		T138	2
all_levels[46]	auto[1]	3	1			T138	1		T238	2		-	-
all_levels[47]	auto[0]	8	1			T139	1		T140	1		T141	2
all_levels[47]	auto[1]	4	1			T214	2		T239	1		T240	1
all_levels[48]	auto[0]	3	1			T142	1		T143	1		T144	1
all_levels[48]	auto[1]	1	1			T142	1		-	-		-	-
all_levels[49]	auto[0]	6	1			T132	1		T145	1		T133	1
all_levels[49]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[50]	auto[0]	9	1			T146	1		T147	1		T148	1
all_levels[50]	auto[1]	2	1			T218	2		-	-		-	-
all_levels[51]	auto[0]	5	1			T149	1		T150	1		T147	1
all_levels[51]	auto[1]	1	1			T163	1		-	-		-	-
all_levels[52]	auto[0]	9	1			T117	1		T129	1		T116	2
all_levels[52]	auto[1]	2	1			T242	1		T243	1		-	-
all_levels[53]	auto[0]	5	1			T116	1		T151	1		T152	1
all_levels[53]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[54]	auto[0]	7	1			T100	1		T153	1		T154	1
all_levels[54]	auto[1]	6	1			T245	4		T246	2		-	-
all_levels[55]	auto[0]	7	1			T155	1		T156	2		T157	1
all_levels[56]	auto[0]	7	1			T15	1		T116	1		T158	1
all_levels[57]	auto[0]	5	1			T129	2		T159	1		T158	1
all_levels[58]	auto[0]	7	1			T116	1		T160	1		T95	1
all_levels[58]	auto[1]	1	1			T217	1		-	-		-	-
all_levels[59]	auto[0]	1	1			T161	1		-	-		-	-
all_levels[60]	auto[0]	2	1			T162	1		T163	1		-	-
all_levels[61]	auto[0]	3	1			T160	1		T164	1		T165	1
all_levels[62]	auto[0]	3	1			T123	1		T166	1		T167	1
all_levels[62]	auto[1]	1	1			T167	1		-	-		-	-
all_levels[63]	auto[0]	6	1			T17	1		T116	1		T154	2
all_levels[64]	auto[0]	61	1			T15	1		T17	1		T129	2
all_levels[64]	auto[1]	12	1			T116	1		T247	1		T245	1