Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	76011	1			T1	1		T3	1		T5	2
all_pins[1]	76011	1			T1	1		T3	1		T5	2
all_pins[2]	76011	1			T1	1		T3	1		T5	2
all_pins[3]	76011	1			T1	1		T3	1		T5	2
all_pins[4]	76011	1			T1	1		T3	1		T5	2
all_pins[5]	76011	1			T1	1		T3	1		T5	2
all_pins[6]	76011	1			T1	1		T3	1		T5	2
all_pins[7]	76011	1			T1	1		T3	1		T5	2
all_pins[8]	76011	1			T1	1		T3	1		T5	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	651658	1			T1	9		T3	9		T5	18
values[0x1]	32441	1			T6	109		T8	59		T11	23
transitions[0x0=>0x1]	24966	1			T6	80		T8	58		T11	19
transitions[0x1=>0x0]	24781	1			T6	81		T8	58		T11	19

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	61121	1			T1	1		T3	1		T5	2
all_pins[0]	values[0x1]	14890	1			T6	68		T11	4		T12	2
all_pins[0]	transitions[0x0=>0x1]	14382	1			T6	56		T11	4		T12	2
all_pins[0]	transitions[0x1=>0x0]	979	1			T6	2		T8	27		T12	4
all_pins[1]	values[0x0]	74524	1			T1	1		T3	1		T5	2
all_pins[1]	values[0x1]	1487	1			T6	14		T8	27		T12	4
all_pins[1]	transitions[0x0=>0x1]	1389	1			T6	14		T8	27		T12	4
all_pins[1]	transitions[0x1=>0x0]	1977	1			T11	3		T14	1		T19	4
all_pins[2]	values[0x0]	73936	1			T1	1		T3	1		T5	2
all_pins[2]	values[0x1]	2075	1			T11	3		T14	1		T19	4
all_pins[2]	transitions[0x0=>0x1]	2027	1			T11	3		T14	1		T19	4
all_pins[2]	transitions[0x1=>0x0]	178	1			T18	1		T99	2		T32	2
all_pins[3]	values[0x0]	75785	1			T1	1		T3	1		T5	2
all_pins[3]	values[0x1]	226	1			T17	2		T18	1		T70	2
all_pins[3]	transitions[0x0=>0x1]	190	1			T17	2		T18	1		T70	2
all_pins[3]	transitions[0x1=>0x0]	397	1			T6	10		T8	8		T70	3
all_pins[4]	values[0x0]	75578	1			T1	1		T3	1		T5	2
all_pins[4]	values[0x1]	433	1			T6	10		T8	8		T70	3
all_pins[4]	transitions[0x0=>0x1]	364	1			T6	9		T8	7		T70	2
all_pins[4]	transitions[0x1=>0x0]	129	1			T18	2		T70	1		T99	1
all_pins[5]	values[0x0]	75813	1			T1	1		T3	1		T5	2
all_pins[5]	values[0x1]	198	1			T6	1		T8	1		T18	2
all_pins[5]	transitions[0x0=>0x1]	170	1			T6	1		T8	1		T18	2
all_pins[5]	transitions[0x1=>0x0]	705	1			T8	8		T19	1		T18	1
all_pins[6]	values[0x0]	75278	1			T1	1		T3	1		T5	2
all_pins[6]	values[0x1]	733	1			T8	8		T19	1		T18	1
all_pins[6]	transitions[0x0=>0x1]	678	1			T8	8		T19	1		T42	1
all_pins[6]	transitions[0x1=>0x0]	290	1			T15	6		T18	2		T70	1
all_pins[7]	values[0x0]	75666	1			T1	1		T3	1		T5	2
all_pins[7]	values[0x1]	345	1			T15	6		T18	3		T70	3
all_pins[7]	transitions[0x0=>0x1]	205	1			T15	6		T18	2		T70	3
all_pins[7]	transitions[0x1=>0x0]	11914	1			T6	16		T8	15		T11	16
all_pins[8]	values[0x0]	63957	1			T1	1		T3	1		T5	2
all_pins[8]	values[0x1]	12054	1			T6	16		T8	15		T11	16
all_pins[8]	transitions[0x0=>0x1]	5561	1			T8	15		T11	12		T12	1
all_pins[8]	transitions[0x1=>0x0]	8212	1			T6	53		T14	4		T15	2