Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	4325747	1			T3	1		T6	37		T8	19
all_levels[1]	1074426	1			T6	135		T11	1		T12	4
all_levels[2]	199750	1			T11	1		T17	1		T41	3
all_levels[3]	146551	1			T11	4		T12	2		T42	6
all_levels[4]	415811	1			T11	3		T12	1		T18	3
all_levels[5]	176780	1			T11	22		T12	3		T15	4
all_levels[6]	191156	1			T11	6		T12	2		T17	4
all_levels[7]	257733	1			T8	11		T15	1		T18	2
all_levels[8]	244439	1			T8	2371		T11	3		T12	3
all_levels[9]	140477	1			T19	1		T41	13		T42	2
all_levels[10]	207544	1			T15	3		T17	1		T18	1
all_levels[11]	238691	1			T17	4		T18	2		T42	5
all_levels[12]	162491	1			T11	2		T15	2		T19	8
all_levels[13]	168378	1			T12	1		T15	1		T17	1
all_levels[14]	167972	1			T19	1		T18	5		T42	3
all_levels[15]	137135	1			T18	2		T42	7		T27	2
all_levels[16]	216374	1			T11	16		T12	1		T17	1
all_levels[17]	147050	1			T12	1		T18	1		T27	2
all_levels[18]	139121	1			T11	9		T18	1		T41	3
all_levels[19]	166392	1			T19	2		T17	2		T18	1
all_levels[20]	220032	1			T11	20		T18	1		T70	1
all_levels[21]	153976	1			T12	1		T71	1		T18	1
all_levels[22]	188882	1			T11	6		T12	1		T39	3
all_levels[23]	122547	1			T15	7		T18	1		T39	4
all_levels[24]	264818	1			T19	3		T18	2		T39	3
all_levels[25]	200576	1			T12	1		T39	3		T27	2
all_levels[26]	572732	1			T11	1		T71	2		T17	1
all_levels[27]	109986	1			T11	1		T71	2		T17	2
all_levels[28]	230301	1			T11	2		T12	1		T39	2
all_levels[29]	107772	1			T39	2		T27	2		T119	3
all_levels[30]	118347	1			T18	1		T27	2		T278	1
all_levels[31]	652358	1			T11	2		T71	4		T18	13
all_levels[32]	9713271	1			T11	33		T12	15		T15	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21575717

1

T6

136

T8

2374

T11

145

auto[1]

3899

1

T3

1

T6

36

T8

27

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	4323509	1			T6	1		T11	13		T12	7
all_levels[0]	auto[1]	2238	1			T3	1		T6	36		T8	19
all_levels[1]	auto[0]	1074154	1			T6	135		T11	1		T12	4
all_levels[1]	auto[1]	272	1			T114	2		T115	1		T116	2
all_levels[2]	auto[0]	199719	1			T11	1		T17	1		T41	1
all_levels[2]	auto[1]	31	1			T41	2		T45	1		T119	1
all_levels[3]	auto[0]	146408	1			T11	4		T12	2		T42	6
all_levels[3]	auto[1]	143	1			T104	23		T290	1		T99	11
all_levels[4]	auto[0]	415781	1			T11	3		T12	1		T18	3
all_levels[4]	auto[1]	30	1			T114	1		T271	1		T159	2
all_levels[5]	auto[0]	176752	1			T11	22		T12	3		T15	4
all_levels[5]	auto[1]	28	1			T187	2		T402	1		T403	1
all_levels[6]	auto[0]	191128	1			T11	6		T12	2		T17	4
all_levels[6]	auto[1]	28	1			T114	1		T404	1		T405	1
all_levels[7]	auto[0]	257645	1			T8	3		T15	1		T18	2
all_levels[7]	auto[1]	88	1			T8	8		T104	3		T273	4
all_levels[8]	auto[0]	244421	1			T8	2371		T11	3		T12	3
all_levels[8]	auto[1]	18	1			T97	1		T177	2		T208	2
all_levels[9]	auto[0]	140445	1			T19	1		T41	13		T42	2
all_levels[9]	auto[1]	32	1			T121	2		T287	1		T139	2
all_levels[10]	auto[0]	207513	1			T15	3		T17	1		T18	1
all_levels[10]	auto[1]	31	1			T406	2		T407	1		T408	4
all_levels[11]	auto[0]	238675	1			T17	4		T18	2		T42	5
all_levels[11]	auto[1]	16	1			T101	1		T409	1		T410	1
all_levels[12]	auto[0]	162464	1			T11	2		T15	2		T19	8
all_levels[12]	auto[1]	27	1			T114	1		T284	1		T265	1
all_levels[13]	auto[0]	168358	1			T12	1		T15	1		T17	1
all_levels[13]	auto[1]	20	1			T125	1		T282	1		T411	1
all_levels[14]	auto[0]	167958	1			T19	1		T18	5		T42	3
all_levels[14]	auto[1]	14	1			T45	1		T285	1		T329	1
all_levels[15]	auto[0]	137036	1			T18	2		T42	7		T27	2
all_levels[15]	auto[1]	99	1			T259	1		T99	12		T255	1
all_levels[16]	auto[0]	216353	1			T11	16		T12	1		T17	1
all_levels[16]	auto[1]	21	1			T317	1		T145	1		T367	1
all_levels[17]	auto[0]	147027	1			T12	1		T18	1		T27	2
all_levels[17]	auto[1]	23	1			T309	1		T402	1		T412	1
all_levels[18]	auto[0]	139103	1			T11	9		T18	1		T41	2
all_levels[18]	auto[1]	18	1			T41	1		T253	1		T125	1
all_levels[19]	auto[0]	166371	1			T19	2		T17	2		T18	1
all_levels[19]	auto[1]	21	1			T114	1		T263	1		T128	1
all_levels[20]	auto[0]	220015	1			T11	20		T18	1		T70	1
all_levels[20]	auto[1]	17	1			T289	1		T170	1		T413	1
all_levels[21]	auto[0]	153957	1			T12	1		T71	1		T18	1
all_levels[21]	auto[1]	19	1			T114	1		T252	1		T414	1
all_levels[22]	auto[0]	188854	1			T11	6		T12	1		T39	3
all_levels[22]	auto[1]	28	1			T33	1		T116	3		T415	1
all_levels[23]	auto[0]	122524	1			T15	7		T18	1		T39	4
all_levels[23]	auto[1]	23	1			T34	1		T416	2		T198	3
all_levels[24]	auto[0]	264791	1			T19	3		T18	2		T39	3
all_levels[24]	auto[1]	27	1			T253	1		T169	3		T269	1
all_levels[25]	auto[0]	200560	1			T12	1		T39	3		T27	2
all_levels[25]	auto[1]	16	1			T349	1		T185	2		T417	2
all_levels[26]	auto[0]	572721	1			T11	1		T71	2		T17	1
all_levels[26]	auto[1]	11	1			T132	2		T342	1		T418	1
all_levels[27]	auto[0]	109972	1			T11	1		T71	2		T17	2
all_levels[27]	auto[1]	14	1			T297	1		T134	2		T139	1
all_levels[28]	auto[0]	230278	1			T11	2		T12	1		T39	2
all_levels[28]	auto[1]	23	1			T419	1		T420	3		T247	2
all_levels[29]	auto[0]	107750	1			T39	2		T27	2		T119	3
all_levels[29]	auto[1]	22	1			T48	2		T421	1		T142	3
all_levels[30]	auto[0]	118333	1			T18	1		T27	2		T278	1
all_levels[30]	auto[1]	14	1			T234	1		T420	2		T422	1
all_levels[31]	auto[0]	652341	1			T11	2		T71	4		T18	13
all_levels[31]	auto[1]	17	1			T101	1		T312	2		T402	1
all_levels[32]	auto[0]	9712801	1			T11	33		T12	15		T15	2
all_levels[32]	auto[1]	470	1			T15	1		T71	1		T39	1