Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	658	1			T18	7		T70	11		T27	4
all_values[1]	658	1			T18	7		T70	11		T27	4
all_values[2]	658	1			T18	7		T70	11		T27	4
all_values[3]	658	1			T18	7		T70	11		T27	4
all_values[4]	658	1			T18	7		T70	11		T27	4
all_values[5]	658	1			T18	7		T70	11		T27	4
all_values[6]	658	1			T18	7		T70	11		T27	4
all_values[7]	658	1			T18	7		T70	11		T27	4
all_values[8]	658	1			T18	7		T70	11		T27	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3214

1

T18

36

T70

50

T27

23

auto[1]

2708

1

T18

27

T70

49

T27

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1956

1

T18

17

T70

29

T27

10

auto[1]

3966

1

T18

46

T70

70

T27

26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3511

1

T18

37

T70

58

T27

26

auto[1]

2411

1

T18

26

T70

41

T27

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	212	1			T18	3		T70	4		T27	1
all_values[0]	auto[0]	auto[1]	auto[1]	168	1			T18	2		T70	3		T27	2
all_values[0]	auto[1]	auto[0]	auto[1]	144	1			T18	1		T70	2		T32	1
all_values[0]	auto[1]	auto[1]	auto[1]	134	1			T18	1		T70	2		T27	1
all_values[1]	auto[0]	auto[0]	auto[0]	214	1			T70	6		T27	2		T32	2
all_values[1]	auto[0]	auto[1]	auto[0]	179	1			T18	4		T70	2		T27	1
all_values[1]	auto[1]	auto[0]	auto[1]	151	1			T18	1		T70	1		T27	1
all_values[1]	auto[1]	auto[1]	auto[1]	114	1			T18	2		T70	2		T34	1
all_values[2]	auto[0]	auto[0]	auto[0]	156	1			T27	1		T32	2		T34	1
all_values[2]	auto[0]	auto[0]	auto[1]	66	1			T70	1		T27	1		T32	1
all_values[2]	auto[0]	auto[1]	auto[0]	110	1			T70	1		T32	2		T106	2
all_values[2]	auto[0]	auto[1]	auto[1]	65	1			T18	3		T70	5		T32	1
all_values[2]	auto[1]	auto[0]	auto[1]	147	1			T18	1		T70	2		T27	2
all_values[2]	auto[1]	auto[1]	auto[1]	114	1			T18	3		T70	2		T32	1
all_values[3]	auto[0]	auto[0]	auto[0]	151	1			T18	2		T70	1		T27	3
all_values[3]	auto[0]	auto[0]	auto[1]	51	1			T70	2		T107	1		T108	1
all_values[3]	auto[0]	auto[1]	auto[0]	118	1			T18	3		T70	1		T27	1
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T32	2		T34	1		T107	1
all_values[3]	auto[1]	auto[0]	auto[1]	138	1			T18	2		T70	4		T107	1
all_values[3]	auto[1]	auto[1]	auto[1]	131	1			T70	3		T32	1		T34	1
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T18	4		T27	1		T32	1
all_values[4]	auto[0]	auto[0]	auto[1]	59	1			T18	1		T70	3		T32	2
all_values[4]	auto[0]	auto[1]	auto[0]	115	1			T70	2		T107	1		T106	2
all_values[4]	auto[0]	auto[1]	auto[1]	60	1			T70	1		T27	2		T32	2
all_values[4]	auto[1]	auto[0]	auto[1]	133	1			T18	2		T70	3		T27	1
all_values[4]	auto[1]	auto[1]	auto[1]	126	1			T70	2		T106	1		T109	1
all_values[5]	auto[0]	auto[0]	auto[0]	136	1			T18	1		T70	1		T32	4
all_values[5]	auto[0]	auto[0]	auto[1]	72	1			T18	1		T70	1		T27	3
all_values[5]	auto[0]	auto[1]	auto[0]	103	1			T70	3		T32	2		T34	1
all_values[5]	auto[0]	auto[1]	auto[1]	66	1			T70	1		T106	1		T109	2
all_values[5]	auto[1]	auto[0]	auto[1]	161	1			T18	2		T70	3		T27	1
all_values[5]	auto[1]	auto[1]	auto[1]	120	1			T18	3		T70	2		T107	1
all_values[6]	auto[0]	auto[0]	auto[0]	150	1			T18	2		T70	3		T34	1
all_values[6]	auto[0]	auto[0]	auto[1]	61	1			T18	1		T32	1		T110	1
all_values[6]	auto[0]	auto[1]	auto[0]	124	1			T18	1		T70	3		T32	2
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T70	2		T27	3		T32	1
all_values[6]	auto[1]	auto[0]	auto[1]	151	1			T18	2		T70	1		T27	1
all_values[6]	auto[1]	auto[1]	auto[1]	107	1			T18	1		T70	2		T32	3
all_values[7]	auto[0]	auto[0]	auto[0]	131	1			T70	2		T27	1		T32	2
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T18	3		T32	1		T107	1
all_values[7]	auto[0]	auto[1]	auto[0]	104	1			T70	4		T34	1		T106	5
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T18	1		T70	1		T27	1
all_values[7]	auto[1]	auto[0]	auto[1]	148	1			T18	3		T70	2		T32	3
all_values[7]	auto[1]	auto[1]	auto[1]	122	1			T70	2		T27	2		T32	1
all_values[8]	auto[0]	auto[0]	auto[1]	200	1			T18	4		T70	3		T27	3
all_values[8]	auto[0]	auto[1]	auto[1]	188	1			T18	1		T70	2		T32	4
all_values[8]	auto[1]	auto[0]	auto[1]	141	1			T70	5		T27	1		T32	1
all_values[8]	auto[1]	auto[1]	auto[1]	129	1			T18	2		T70	1		T32	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal