Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 13 0 13 100.00
Crosses 36 0 36 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 9 0 9 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 36 0 36 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 9 0 9 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 91797 1 T1 1 T2 26 T3 2
all_values[1] 91797 1 T1 1 T2 26 T3 2
all_values[2] 91797 1 T1 1 T2 26 T3 2
all_values[3] 91797 1 T1 1 T2 26 T3 2
all_values[4] 91797 1 T1 1 T2 26 T3 2
all_values[5] 91797 1 T1 1 T2 26 T3 2
all_values[6] 91797 1 T1 1 T2 26 T3 2
all_values[7] 91797 1 T1 1 T2 26 T3 2
all_values[8] 91797 1 T1 1 T2 26 T3 2



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 415062 1 T1 4 T2 160 T3 18
auto[1] 411111 1 T1 5 T2 74 T6 6



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 747110 1 T1 7 T2 185 T3 13
auto[1] 79063 1 T1 2 T2 49 T3 5



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 36 0 36 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 27219 1 T2 7 T11 1 T19 1
all_values[0] auto[0] auto[1] 20072 1 T2 12 T3 2 T7 2
all_values[0] auto[1] auto[0] 25241 1 T2 5 T11 7 T19 11
all_values[0] auto[1] auto[1] 19265 1 T1 1 T2 2 T6 1
all_values[1] auto[0] auto[0] 47323 1 T2 14 T3 2 T7 2
all_values[1] auto[0] auto[1] 1148 1 T12 6 T19 8 T20 16
all_values[1] auto[1] auto[0] 42178 1 T1 1 T6 1 T11 9
all_values[1] auto[1] auto[1] 1148 1 T2 12 T21 8 T32 2
all_values[2] auto[0] auto[0] 42758 1 T2 17 T3 1 T7 1
all_values[2] auto[0] auto[1] 2318 1 T2 7 T3 1 T7 1
all_values[2] auto[1] auto[0] 44743 1 T1 1 T2 1 T6 1
all_values[2] auto[1] auto[1] 1978 1 T2 1 T11 1 T17 1
all_values[3] auto[0] auto[0] 40483 1 T1 1 T2 21 T3 2
all_values[3] auto[0] auto[1] 229 1 T2 3 T20 1 T23 3
all_values[3] auto[1] auto[0] 50827 1 T2 2 T6 1 T11 11
all_values[3] auto[1] auto[1] 258 1 T19 1 T276 1 T76 2
all_values[4] auto[0] auto[0] 43440 1 T2 7 T3 2 T6 1
all_values[4] auto[0] auto[1] 376 1 T20 1 T26 10 T38 2
all_values[4] auto[1] auto[0] 47645 1 T1 1 T2 19 T11 11
all_values[4] auto[1] auto[1] 336 1 T21 5 T22 9 T23 2
all_values[5] auto[0] auto[0] 47167 1 T1 1 T2 17 T3 2
all_values[5] auto[0] auto[1] 176 1 T38 1 T78 1 T121 3
all_values[5] auto[1] auto[0] 44304 1 T2 9 T13 1 T29 19
all_values[5] auto[1] auto[1] 150 1 T38 4 T77 2 T78 1
all_values[6] auto[0] auto[0] 48845 1 T1 1 T2 12 T3 2
all_values[6] auto[0] auto[1] 162 1 T23 2 T38 5 T78 3
all_values[6] auto[1] auto[0] 42607 1 T2 14 T11 8 T13 1
all_values[6] auto[1] auto[1] 183 1 T38 4 T76 3 T118 3
all_values[7] auto[0] auto[0] 43012 1 T2 24 T3 2 T7 2
all_values[7] auto[0] auto[1] 380 1 T22 6 T31 1 T26 1
all_values[7] auto[1] auto[0] 48124 1 T1 1 T2 2 T6 1
all_values[7] auto[1] auto[1] 281 1 T21 4 T107 2 T277 1
all_values[8] auto[0] auto[0] 34245 1 T2 9 T11 1 T19 11
all_values[8] auto[0] auto[1] 15709 1 T1 1 T2 10 T3 2
all_values[8] auto[1] auto[0] 26949 1 T2 5 T11 8 T19 1
all_values[8] auto[1] auto[1] 14894 1 T2 2 T6 1 T29 19

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