Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.08 97.65 100.00 98.35 100.00 99.62


Total tests in report: 1314
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
71.82 71.82 94.29 94.29 77.41 77.41 63.26 63.26 91.06 91.06 94.69 94.69 10.23 10.23 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.1226577108
79.79 7.97 94.90 0.61 84.00 6.59 94.82 31.57 93.41 2.35 94.69 0.00 16.93 6.71 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_fifo_reset.2934967020
83.65 3.85 97.65 2.76 93.53 9.53 96.97 2.15 96.00 2.59 96.17 1.47 21.56 4.63 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.2529714818
85.64 1.99 97.65 0.00 93.53 0.00 96.97 0.00 96.00 0.00 96.17 0.00 33.51 11.94 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_stress_all.3145900777
87.47 1.83 97.65 0.00 93.53 0.00 96.97 0.00 96.00 0.00 96.17 0.00 44.50 11.00 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1272072341
88.87 1.40 97.65 0.00 93.53 0.00 96.97 0.00 96.00 0.00 96.46 0.29 52.61 8.11 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_stress_all.763871102
90.07 1.20 97.65 0.00 93.53 0.00 96.97 0.00 96.00 0.00 96.46 0.00 59.81 7.20 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_stress_all.1947339213
90.91 0.84 97.65 0.00 94.00 0.47 97.22 0.25 96.00 0.00 96.46 0.00 64.10 4.29 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.864596570
91.65 0.75 97.65 0.00 94.00 0.00 97.22 0.00 96.00 0.00 96.46 0.00 68.57 4.47 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.2378229274
92.27 0.62 97.96 0.31 95.53 1.53 97.22 0.00 96.94 0.94 96.46 0.00 69.52 0.95 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_intr.3946557102
92.88 0.61 98.06 0.10 95.88 0.35 99.75 2.53 97.18 0.24 96.76 0.29 69.65 0.14 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_sec_cm.3118056519
93.47 0.59 98.06 0.00 95.88 0.00 99.75 0.00 97.18 0.00 96.76 0.00 73.18 3.52 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.8463463
94.01 0.54 98.88 0.82 96.24 0.35 99.75 0.00 98.12 0.94 96.76 0.00 74.31 1.13 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1266786636
94.48 0.48 98.88 0.00 96.24 0.00 99.75 0.00 98.12 0.00 96.76 0.00 77.17 2.87 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_noise_filter.2332035439
94.92 0.44 99.08 0.20 96.47 0.24 99.75 0.00 98.35 0.24 96.76 0.00 79.14 1.96 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_rx_oversample.3923539439
95.35 0.42 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 97.05 0.29 81.37 2.24 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_fifo_reset.1859885179
95.68 0.33 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 97.05 0.00 83.38 2.01 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_stress_all.22474645
95.98 0.29 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 98.82 1.77 83.38 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.3322500191
96.24 0.26 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 98.82 0.00 84.96 1.58 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.75436432
96.48 0.24 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 98.82 0.00 86.41 1.45 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.3875802764
96.71 0.23 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.88 86.88 0.47 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.2299177663
96.93 0.23 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.00 88.24 1.35 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_fifo_reset.793868352
97.15 0.21 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.00 89.52 1.29 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_stress_all.1656149931
97.31 0.17 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.00 90.52 0.99 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.81435788
97.46 0.15 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.00 91.40 0.88 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1805795786
97.60 0.14 99.08 0.00 97.18 0.71 99.75 0.00 98.35 0.00 99.71 0.00 91.56 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3852014217
97.74 0.14 99.08 0.00 97.18 0.00 99.75 0.00 98.35 0.00 99.71 0.00 92.39 0.84 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.2501796
97.86 0.12 99.08 0.00 97.18 0.00 99.75 0.00 98.35 0.00 99.71 0.00 93.09 0.70 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_stress_all.224091557
97.96 0.10 99.08 0.00 97.53 0.35 100.00 0.25 98.35 0.00 99.71 0.00 93.11 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_alert_test.1762089786
98.05 0.09 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 99.71 0.00 93.63 0.52 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.90797749
98.11 0.06 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 99.71 0.00 94.02 0.38 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_fifo_reset.2406898493
98.17 0.06 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 99.71 0.00 94.38 0.36 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_fifo_reset.1715576110
98.23 0.06 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 99.71 0.00 94.74 0.36 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_fifo_reset.2038608598
98.29 0.05 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 99.71 0.00 95.06 0.32 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.3499950221
98.34 0.05 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.29 95.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.2980273550
98.39 0.05 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 95.35 0.29 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.4119877594
98.43 0.05 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 95.62 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_fifo_full.3775452206
98.47 0.04 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 95.87 0.25 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_fifo_reset.1982443931
98.51 0.04 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.09 0.23 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_fifo_full.2472184206
98.54 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.30 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_stress_all.2695254900
98.58 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.50 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/22.uart_fifo_reset.577809901
98.60 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.66 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3320027035
98.63 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.82 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/166.uart_fifo_reset.662992791
98.66 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.97 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/33.uart_intr.3862395068
98.68 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.13 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_fifo_reset.3035426992
98.71 0.02 99.08 0.00 97.65 0.12 100.00 0.00 98.35 0.00 100.00 0.00 97.16 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3084840351
98.73 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.29 0.14 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_tx_rx.4237774286
98.75 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.43 0.14 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.3968557020
98.77 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.54 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_smoke.3691639655
98.79 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.65 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/150.uart_fifo_reset.3795831174
98.81 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.76 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3089754414
98.83 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.88 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_fifo_reset.4086480336
98.84 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.97 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_tx_rx.2741203470
98.86 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.06 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_stress_all.2268594931
98.87 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.15 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/161.uart_fifo_reset.637565490
98.89 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.24 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/190.uart_fifo_reset.238811300
98.90 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.33 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/30.uart_fifo_reset.2473636754
98.91 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.40 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.219826975
98.92 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.46 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_noise_filter.1207156983
98.94 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.53 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/149.uart_fifo_reset.1808988946
98.95 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.60 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/156.uart_fifo_reset.3616832606
98.96 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.67 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/176.uart_fifo_reset.3697608998
98.97 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.74 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_perf.2910779063
98.98 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.78 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2590658400
98.98 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.83 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_stress_all.4193248395
98.99 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.87 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.3203800595
99.00 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.92 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/138.uart_fifo_reset.3666568311
99.01 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/163.uart_fifo_reset.2600530751
99.01 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/221.uart_fifo_reset.2916226798
99.02 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.05 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/227.uart_fifo_reset.4157686024
99.03 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.10 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/251.uart_fifo_reset.245340728
99.04 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.14 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/27.uart_stress_all.2084981170
99.04 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.19 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/70.uart_fifo_reset.110603514
99.05 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.23 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/99.uart_fifo_reset.3466077941
99.06 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.25 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2840574655
99.06 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.28 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_noise_filter.368286402
99.06 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.30 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/101.uart_fifo_reset.2526168516
99.07 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.32 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/103.uart_fifo_reset.855450167
99.07 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.35 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/105.uart_fifo_reset.1913790607
99.07 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.37 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/124.uart_fifo_reset.1297060715
99.08 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.39 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/126.uart_fifo_reset.1403972485
99.08 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.41 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/160.uart_fifo_reset.149357554
99.09 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.44 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/165.uart_fifo_reset.3226457278
99.09 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.46 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2913794692
99.09 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.48 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3484759799
99.10 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.50 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_stress_all.2687480261
99.10 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.53 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/213.uart_fifo_reset.3327322569
99.11 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.55 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/215.uart_fifo_reset.2077878459
99.11 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.57 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/240.uart_fifo_reset.376310776
99.11 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.59 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/276.uart_fifo_reset.4125939000
99.12 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.62 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/53.uart_fifo_reset.457165970

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2632253707
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1928376366
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.955120868
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1889705283
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.3044844188
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2165877866
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.983829328
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.2692253460
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3213020821
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3265081677
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3790604405
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3611930461
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3340505520
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.769599274
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1455409914
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.899906559
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.144845319
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1482244979
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.1605271345
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1713699915
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1102165087
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1733439680
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3264247910
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3043855303
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.1287062189
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2835081882
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.536100927
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2719062045
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2503933268
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.2986874603
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.351281829
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3466290452
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.302521535
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.1422877903
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.2660462562
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2860650733
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1135552149
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.2369508390
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4281150888
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1210251200
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.2288747743
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1909957392
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.460864832
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3072621589
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3616665106
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.650027420
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3067586021
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2039182067
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.2073989537
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.3051005735
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3164805583
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.3359177756
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.563430794
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1946511865
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.274645192
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.941780210
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4264868096
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2691274961
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.3416573891
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3091968705
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3296615705
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3397094399
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2304677942
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.718344352
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3165424848
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.1224083708
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1363476358
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.85944000
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.192362029
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.982987409
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2948271494
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2117431134
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1365898085
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3893640458
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3175953822
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.3458009527
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.630438898
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1892578584
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3134913079
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.1719035597
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3559456919
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.560977436
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3447143528
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2623722874
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.475701270
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.866629871
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.2167606655
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3233102416
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.965465337
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.1036349266
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.3259958006
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.3993387357
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2351038997
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.568300069
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.545352369
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.806436234
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3971492129
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.125077685
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.1938496104
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1362033776
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.3279484759
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.358301678
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1097449041
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2807994452
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2165962056
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3030968462
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.4050267931
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.1451160197
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.91589531
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2260005801
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3265733552
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2777274914
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2492566652
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3750737589
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.255854582
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1204061556
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.2393858980
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.4061088170
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.1604424081
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3740218098
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1442295392
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1332529586
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.2718720078
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.3792637927
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.2408518042
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.823704779
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.3205712704
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.1437350631
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.2447166200
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2090322514
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.2057829514
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1433258363
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.3302234372
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.1543072978
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1580064015
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.3627116307
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.2684708774
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3010261333
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.867114483
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.3258781349
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.3452124526
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3907462173
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/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1042268842
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2058456803
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/76.uart_fifo_reset.1493464858
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.2403046124
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/77.uart_fifo_reset.3732067724
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.220796743
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/78.uart_fifo_reset.791907345
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.1322635358
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/79.uart_fifo_reset.3234767463
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.1351640487
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_alert_test.67262792
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_fifo_full.4184600064
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_fifo_reset.2490289916
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.2795612956
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_loopback.824961329
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_noise_filter.1185603
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_perf.1930271314
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_rx_oversample.3983871779
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.2243567586
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_smoke.2728080550
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_stress_all.1549791307
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1921788985
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1015252685
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_tx_rx.1046963050
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/80.uart_fifo_reset.3565133482
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.3558576488
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/81.uart_fifo_reset.2250401150
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.2651006540
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/82.uart_fifo_reset.1441628367
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.640009103
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/83.uart_fifo_reset.2825166723
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.3788174834
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/84.uart_fifo_reset.596217924
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.4236824615
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/85.uart_fifo_reset.384640306
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.1922596010
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/86.uart_fifo_reset.1946393857
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.2771601981
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/87.uart_fifo_reset.2125307936
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.2698878451
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/88.uart_fifo_reset.4264247177
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.797301144
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2652848935
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.3041050410
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_alert_test.3486021285
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_fifo_full.3728671241
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3576355995
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_intr.707749106
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.1944076153
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_loopback.3619476084
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_noise_filter.2897454122
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_perf.978200640
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2184920025
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.1091741367
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.2739452264
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_smoke.1196478991
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_stress_all.1881873365
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3073299342
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.2390614055
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_tx_rx.2858196195
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/90.uart_fifo_reset.2698378052
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.783973318
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/91.uart_fifo_reset.788216153
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.3645658136
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3058889618
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.2897526368
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2152097832
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.1186680340
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/94.uart_fifo_reset.3144570262
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.2318513563
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/95.uart_fifo_reset.706250431
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.1577186000
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/96.uart_fifo_reset.1946512150
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.68638299
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/97.uart_fifo_reset.225653074
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.3164769184
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/98.uart_fifo_reset.1201794517
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.3796970072
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.1014227930



Total test records in report: 1314
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2491185498 Oct 12 01:29:02 PM UTC 24 Oct 12 01:29:06 PM UTC 24 3251539486 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.1226577108 Oct 12 01:29:01 PM UTC 24 Oct 12 01:29:08 PM UTC 24 11510114092 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.2993165467 Oct 12 01:29:04 PM UTC 24 Oct 12 01:29:08 PM UTC 24 879738061 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_alert_test.2111401700 Oct 12 01:29:07 PM UTC 24 Oct 12 01:29:08 PM UTC 24 31466542 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_sec_cm.420097880 Oct 12 01:29:07 PM UTC 24 Oct 12 01:29:08 PM UTC 24 153452273 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_loopback.1333358568 Oct 12 01:29:09 PM UTC 24 Oct 12 01:29:11 PM UTC 24 200022579 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.3051167058 Oct 12 01:29:09 PM UTC 24 Oct 12 01:29:12 PM UTC 24 469414899 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_alert_test.1762089786 Oct 12 01:29:11 PM UTC 24 Oct 12 01:29:13 PM UTC 24 13221386 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_sec_cm.3118056519 Oct 12 01:29:11 PM UTC 24 Oct 12 01:29:13 PM UTC 24 62708233 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_smoke.2027405055 Oct 12 01:29:11 PM UTC 24 Oct 12 01:29:16 PM UTC 24 525871257 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2000730686 Oct 12 01:29:01 PM UTC 24 Oct 12 01:29:16 PM UTC 24 18250731784 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_loopback.2282149727 Oct 12 01:29:04 PM UTC 24 Oct 12 01:29:16 PM UTC 24 9911277821 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_smoke.3691639655 Oct 12 01:29:07 PM UTC 24 Oct 12 01:29:17 PM UTC 24 6075327901 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_intr.1665387511 Oct 12 01:29:02 PM UTC 24 Oct 12 01:29:17 PM UTC 24 13195122461 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_rx_oversample.2708019929 Oct 12 01:29:13 PM UTC 24 Oct 12 01:29:17 PM UTC 24 2344899710 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_smoke.1555349923 Oct 12 01:29:01 PM UTC 24 Oct 12 01:29:17 PM UTC 24 11056038158 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_noise_filter.368286402 Oct 12 01:29:09 PM UTC 24 Oct 12 01:29:18 PM UTC 24 7026184346 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_rx_oversample.3923539439 Oct 12 01:29:09 PM UTC 24 Oct 12 01:29:18 PM UTC 24 3472977047 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.1129291082 Oct 12 01:29:09 PM UTC 24 Oct 12 01:29:19 PM UTC 24 5432848153 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3021113921 Oct 12 01:29:15 PM UTC 24 Oct 12 01:29:19 PM UTC 24 2043562579 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_alert_test.2346126769 Oct 12 01:29:18 PM UTC 24 Oct 12 01:29:20 PM UTC 24 34505269 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_sec_cm.1545291424 Oct 12 01:29:18 PM UTC 24 Oct 12 01:29:20 PM UTC 24 57239984 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_rx_oversample.1630055559 Oct 12 01:29:20 PM UTC 24 Oct 12 01:29:26 PM UTC 24 2014133511 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_loopback.1553832376 Oct 12 01:29:15 PM UTC 24 Oct 12 01:29:27 PM UTC 24 3489682169 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.367541384 Oct 12 01:29:21 PM UTC 24 Oct 12 01:29:29 PM UTC 24 2073522138 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_fifo_full.1859271144 Oct 12 01:29:13 PM UTC 24 Oct 12 01:29:29 PM UTC 24 28274279064 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2667137166 Oct 12 01:29:26 PM UTC 24 Oct 12 01:29:29 PM UTC 24 491707179 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_fifo_reset.2934967020 Oct 12 01:29:13 PM UTC 24 Oct 12 01:29:31 PM UTC 24 85033052485 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_sec_cm.940105421 Oct 12 01:29:29 PM UTC 24 Oct 12 01:29:32 PM UTC 24 64955466 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_alert_test.1739362619 Oct 12 01:29:31 PM UTC 24 Oct 12 01:29:32 PM UTC 24 242862223 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_smoke.4280577450 Oct 12 01:29:31 PM UTC 24 Oct 12 01:29:34 PM UTC 24 474105116 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_intr.1831168029 Oct 12 01:29:13 PM UTC 24 Oct 12 01:29:34 PM UTC 24 18947646257 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.1049956664 Oct 12 01:29:10 PM UTC 24 Oct 12 01:29:35 PM UTC 24 2132307767 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_tx_rx.4237774286 Oct 12 01:29:12 PM UTC 24 Oct 12 01:29:36 PM UTC 24 47500109386 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_loopback.1707086477 Oct 12 01:29:27 PM UTC 24 Oct 12 01:29:36 PM UTC 24 3504628170 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.2888642621 Oct 12 01:29:35 PM UTC 24 Oct 12 01:29:38 PM UTC 24 490946212 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.2283069988 Oct 12 01:29:03 PM UTC 24 Oct 12 01:29:39 PM UTC 24 43042496825 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.3660482409 Oct 12 01:29:36 PM UTC 24 Oct 12 01:29:40 PM UTC 24 2137809066 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_intr.940464067 Oct 12 01:29:34 PM UTC 24 Oct 12 01:29:43 PM UTC 24 19326170735 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1329028583 Oct 12 01:29:04 PM UTC 24 Oct 12 01:29:43 PM UTC 24 1383945866 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_sec_cm.1532851743 Oct 12 01:29:41 PM UTC 24 Oct 12 01:29:43 PM UTC 24 217443044 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_tx_rx.1393250158 Oct 12 01:29:01 PM UTC 24 Oct 12 01:29:46 PM UTC 24 56146255144 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_alert_test.1025647519 Oct 12 01:29:44 PM UTC 24 Oct 12 01:29:46 PM UTC 24 36277016 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_loopback.2720181859 Oct 12 01:29:38 PM UTC 24 Oct 12 01:29:47 PM UTC 24 7837559607 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_smoke.426724989 Oct 12 01:29:18 PM UTC 24 Oct 12 01:29:47 PM UTC 24 11051002516 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_smoke.711125718 Oct 12 01:29:44 PM UTC 24 Oct 12 01:29:48 PM UTC 24 689754930 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.2479321724 Oct 12 01:29:09 PM UTC 24 Oct 12 01:29:52 PM UTC 24 52447220287 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.2776181562 Oct 12 01:29:28 PM UTC 24 Oct 12 01:29:55 PM UTC 24 7630782102 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_fifo_full.2828519254 Oct 12 01:29:33 PM UTC 24 Oct 12 01:29:58 PM UTC 24 100785628313 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_tx_rx.4228558883 Oct 12 01:29:44 PM UTC 24 Oct 12 01:29:59 PM UTC 24 4452023876 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_intr.3338473645 Oct 12 01:29:48 PM UTC 24 Oct 12 01:29:59 PM UTC 24 10665637626 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_noise_filter.2332035439 Oct 12 01:29:02 PM UTC 24 Oct 12 01:30:02 PM UTC 24 139316115358 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_fifo_reset.4086480336 Oct 12 01:29:19 PM UTC 24 Oct 12 01:30:02 PM UTC 24 35039884704 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.1928679535 Oct 12 01:30:00 PM UTC 24 Oct 12 01:30:04 PM UTC 24 1663300792 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.525959140 Oct 12 01:29:13 PM UTC 24 Oct 12 01:30:06 PM UTC 24 38874323860 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.3211408769 Oct 12 01:29:13 PM UTC 24 Oct 12 01:30:06 PM UTC 24 80765132434 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.320506663 Oct 12 01:29:57 PM UTC 24 Oct 12 01:30:07 PM UTC 24 2647012686 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_loopback.1721816951 Oct 12 01:30:00 PM UTC 24 Oct 12 01:30:07 PM UTC 24 1286843557 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_alert_test.2714127073 Oct 12 01:30:06 PM UTC 24 Oct 12 01:30:08 PM UTC 24 15152858 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_intr.2256358058 Oct 12 01:29:09 PM UTC 24 Oct 12 01:30:09 PM UTC 24 26640065747 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_fifo_full.2472184206 Oct 12 01:29:18 PM UTC 24 Oct 12 01:30:11 PM UTC 24 57334379637 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_smoke.2044547836 Oct 12 01:30:07 PM UTC 24 Oct 12 01:30:12 PM UTC 24 454663602 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_fifo_reset.3035426992 Oct 12 01:29:34 PM UTC 24 Oct 12 01:30:12 PM UTC 24 9652172490 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1266786636 Oct 12 01:29:17 PM UTC 24 Oct 12 01:30:13 PM UTC 24 2437891791 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_tx_rx.2491665252 Oct 12 01:30:07 PM UTC 24 Oct 12 01:30:15 PM UTC 24 7722610909 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_fifo_reset.1859885179 Oct 12 01:29:47 PM UTC 24 Oct 12 01:30:16 PM UTC 24 211354422300 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.1113888562 Oct 12 01:29:26 PM UTC 24 Oct 12 01:30:16 PM UTC 24 17986224502 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_intr.596956490 Oct 12 01:29:21 PM UTC 24 Oct 12 01:30:18 PM UTC 24 184965028351 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_rx_oversample.196795817 Oct 12 01:30:13 PM UTC 24 Oct 12 01:30:19 PM UTC 24 2421962981 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.1770559984 Oct 12 01:30:16 PM UTC 24 Oct 12 01:30:20 PM UTC 24 1844350393 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_tx_rx.1377142449 Oct 12 01:29:18 PM UTC 24 Oct 12 01:30:24 PM UTC 24 67463488908 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_tx_rx.607198528 Oct 12 01:29:32 PM UTC 24 Oct 12 01:30:24 PM UTC 24 72674271024 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_fifo_full.1396988775 Oct 12 01:29:09 PM UTC 24 Oct 12 01:30:26 PM UTC 24 97402155784 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_fifo_full.1532717246 Oct 12 01:29:46 PM UTC 24 Oct 12 01:30:26 PM UTC 24 21551475156 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_perf.1294570288 Oct 12 01:29:39 PM UTC 24 Oct 12 01:30:27 PM UTC 24 7179027162 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_loopback.334877464 Oct 12 01:30:19 PM UTC 24 Oct 12 01:30:28 PM UTC 24 10563524354 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_alert_test.141382317 Oct 12 01:30:27 PM UTC 24 Oct 12 01:30:28 PM UTC 24 36677161 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.2529714818 Oct 12 01:29:39 PM UTC 24 Oct 12 01:30:29 PM UTC 24 1597002862 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_noise_filter.2420432643 Oct 12 01:29:21 PM UTC 24 Oct 12 01:30:32 PM UTC 24 71109655793 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_smoke.1933760888 Oct 12 01:30:27 PM UTC 24 Oct 12 01:30:33 PM UTC 24 933151260 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_noise_filter.2469759962 Oct 12 01:30:14 PM UTC 24 Oct 12 01:30:35 PM UTC 24 34835879843 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.2887370958 Oct 12 01:30:17 PM UTC 24 Oct 12 01:30:36 PM UTC 24 7160238470 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_noise_filter.3896473212 Oct 12 01:29:53 PM UTC 24 Oct 12 01:30:37 PM UTC 24 14956382717 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_rx_oversample.2794084058 Oct 12 01:29:34 PM UTC 24 Oct 12 01:30:38 PM UTC 24 6888100355 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_rx_oversample.2055961421 Oct 12 01:30:30 PM UTC 24 Oct 12 01:30:39 PM UTC 24 1798961164 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.580079062 Oct 12 01:29:59 PM UTC 24 Oct 12 01:30:39 PM UTC 24 28465442178 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.452125614 Oct 12 01:29:04 PM UTC 24 Oct 12 01:30:40 PM UTC 24 204819684111 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_fifo_reset.1667022385 Oct 12 01:30:12 PM UTC 24 Oct 12 01:30:40 PM UTC 24 38734968439 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.3630989639 Oct 12 01:30:37 PM UTC 24 Oct 12 01:30:41 PM UTC 24 851472642 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_alert_test.2725234231 Oct 12 01:30:42 PM UTC 24 Oct 12 01:30:44 PM UTC 24 23645194 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_loopback.3404784960 Oct 12 01:30:39 PM UTC 24 Oct 12 01:30:46 PM UTC 24 2875242674 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.2413224746 Oct 12 01:30:16 PM UTC 24 Oct 12 01:30:50 PM UTC 24 12583407044 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.1022805616 Oct 12 01:30:36 PM UTC 24 Oct 12 01:30:48 PM UTC 24 2655586363 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_tx_rx.3504956203 Oct 12 01:29:08 PM UTC 24 Oct 12 01:30:52 PM UTC 24 63172779981 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_tx_rx.1941240807 Oct 12 01:30:28 PM UTC 24 Oct 12 01:30:54 PM UTC 24 122238413901 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_smoke.2728080550 Oct 12 01:30:45 PM UTC 24 Oct 12 01:30:55 PM UTC 24 5336791620 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.838274120 Oct 12 01:30:24 PM UTC 24 Oct 12 01:30:56 PM UTC 24 1655020707 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.3617744898 Oct 12 01:30:41 PM UTC 24 Oct 12 01:31:07 PM UTC 24 7250205667 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_rx_oversample.3362682949 Oct 12 01:29:48 PM UTC 24 Oct 12 01:31:13 PM UTC 24 7576838423 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.2894432912 Oct 12 01:30:29 PM UTC 24 Oct 12 01:31:13 PM UTC 24 18041298618 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_noise_filter.496011640 Oct 12 01:29:13 PM UTC 24 Oct 12 01:31:17 PM UTC 24 239781314219 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.2243567586 Oct 12 01:31:08 PM UTC 24 Oct 12 01:31:17 PM UTC 24 3164626141 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.3499950221 Oct 12 01:29:46 PM UTC 24 Oct 12 01:31:19 PM UTC 24 297068840913 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_loopback.824961329 Oct 12 01:31:18 PM UTC 24 Oct 12 01:31:22 PM UTC 24 3886538582 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_fifo_reset.2490289916 Oct 12 01:30:52 PM UTC 24 Oct 12 01:31:23 PM UTC 24 11824127118 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_alert_test.67262792 Oct 12 01:31:24 PM UTC 24 Oct 12 01:31:26 PM UTC 24 15101371 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_smoke.1196478991 Oct 12 01:31:27 PM UTC 24 Oct 12 01:31:30 PM UTC 24 523338915 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_fifo_reset.793868352 Oct 12 01:30:29 PM UTC 24 Oct 12 01:31:35 PM UTC 24 34979786547 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.864596570 Oct 12 01:29:36 PM UTC 24 Oct 12 01:31:36 PM UTC 24 57478057124 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1015252685 Oct 12 01:31:14 PM UTC 24 Oct 12 01:31:39 PM UTC 24 6693261491 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2590658400 Oct 12 01:29:09 PM UTC 24 Oct 12 01:31:40 PM UTC 24 168632035127 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_fifo_full.2055427836 Oct 12 01:30:09 PM UTC 24 Oct 12 01:31:41 PM UTC 24 70242915460 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1805795786 Oct 12 01:30:51 PM UTC 24 Oct 12 01:31:43 PM UTC 24 64967577307 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_rx_oversample.3983871779 Oct 12 01:30:54 PM UTC 24 Oct 12 01:31:50 PM UTC 24 5907033097 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_perf.446903854 Oct 12 01:29:04 PM UTC 24 Oct 12 01:31:52 PM UTC 24 11045738168 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1921788985 Oct 12 01:31:23 PM UTC 24 Oct 12 01:31:55 PM UTC 24 2580503999 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.4252430169 Oct 12 01:29:10 PM UTC 24 Oct 12 01:32:00 PM UTC 24 231589229863 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_noise_filter.1185603 Oct 12 01:30:56 PM UTC 24 Oct 12 01:32:01 PM UTC 24 81663917209 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.2390614055 Oct 12 01:31:56 PM UTC 24 Oct 12 01:32:02 PM UTC 24 2418641342 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/5.uart_perf.3263702888 Oct 12 01:30:03 PM UTC 24 Oct 12 01:32:03 PM UTC 24 11299929199 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.2739452264 Oct 12 01:31:51 PM UTC 24 Oct 12 01:32:06 PM UTC 24 6352634412 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_fifo_full.4081451542 Oct 12 01:30:28 PM UTC 24 Oct 12 01:32:07 PM UTC 24 134288190393 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_loopback.3619476084 Oct 12 01:32:00 PM UTC 24 Oct 12 01:32:08 PM UTC 24 1511883349 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_alert_test.3486021285 Oct 12 01:32:09 PM UTC 24 Oct 12 01:32:10 PM UTC 24 30531343 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_intr.3993175194 Oct 12 01:30:33 PM UTC 24 Oct 12 01:32:13 PM UTC 24 29638061516 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_intr.3946557102 Oct 12 01:30:56 PM UTC 24 Oct 12 01:32:17 PM UTC 24 27391495711 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3073299342 Oct 12 01:32:03 PM UTC 24 Oct 12 01:32:18 PM UTC 24 5857277670 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_smoke.3854462212 Oct 12 01:32:09 PM UTC 24 Oct 12 01:32:25 PM UTC 24 6095379014 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.2823417562 Oct 12 01:29:19 PM UTC 24 Oct 12 01:32:30 PM UTC 24 250224406248 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_fifo_reset.2038608598 Oct 12 01:31:40 PM UTC 24 Oct 12 01:32:32 PM UTC 24 28189160420 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_stress_all.1348332261 Oct 12 01:29:29 PM UTC 24 Oct 12 01:32:32 PM UTC 24 117605434018 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2184920025 Oct 12 01:31:42 PM UTC 24 Oct 12 01:32:32 PM UTC 24 5117642750 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.2918162803 Oct 12 01:30:21 PM UTC 24 Oct 12 01:32:37 PM UTC 24 107101367220 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1272072341 Oct 12 01:29:04 PM UTC 24 Oct 12 01:32:38 PM UTC 24 68215738619 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_stress_all.2687480261 Oct 12 01:29:17 PM UTC 24 Oct 12 01:32:42 PM UTC 24 244768536214 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_rx_oversample.3916581232 Oct 12 01:32:26 PM UTC 24 Oct 12 01:32:42 PM UTC 24 3480330105 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.8463463 Oct 12 01:29:33 PM UTC 24 Oct 12 01:32:42 PM UTC 24 356902107754 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.1091741367 Oct 12 01:31:53 PM UTC 24 Oct 12 01:32:45 PM UTC 24 27211772532 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.4283717686 Oct 12 01:32:32 PM UTC 24 Oct 12 01:32:46 PM UTC 24 4156481027 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_intr.707749106 Oct 12 01:31:43 PM UTC 24 Oct 12 01:32:47 PM UTC 24 17994763266 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_alert_test.3963534709 Oct 12 01:32:46 PM UTC 24 Oct 12 01:32:48 PM UTC 24 31482006 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_smoke.962220918 Oct 12 01:32:47 PM UTC 24 Oct 12 01:32:53 PM UTC 24 694197980 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_fifo_full.3919924051 Oct 12 01:32:14 PM UTC 24 Oct 12 01:32:54 PM UTC 24 38311182756 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_fifo_reset.3798393167 Oct 12 01:32:19 PM UTC 24 Oct 12 01:32:54 PM UTC 24 18414289513 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_rx_oversample.3565546273 Oct 12 01:32:54 PM UTC 24 Oct 12 01:32:59 PM UTC 24 7260869043 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.1418934054 Oct 12 01:32:33 PM UTC 24 Oct 12 01:33:04 PM UTC 24 11660567067 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_fifo_full.4184600064 Oct 12 01:30:49 PM UTC 24 Oct 12 01:33:05 PM UTC 24 83416019244 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_loopback.976949341 Oct 12 01:32:39 PM UTC 24 Oct 12 01:33:08 PM UTC 24 7196888295 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_noise_filter.2313462503 Oct 12 01:30:34 PM UTC 24 Oct 12 01:33:08 PM UTC 24 80362413542 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.304303227 Oct 12 01:33:05 PM UTC 24 Oct 12 01:33:09 PM UTC 24 4116479876 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_fifo_reset.1982443931 Oct 12 01:32:54 PM UTC 24 Oct 12 01:33:14 PM UTC 24 31602113014 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.3707550354 Oct 12 01:33:08 PM UTC 24 Oct 12 01:33:16 PM UTC 24 1435842593 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_stress_all.763871102 Oct 12 01:29:05 PM UTC 24 Oct 12 01:33:17 PM UTC 24 85234364679 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_perf.2637691464 Oct 12 01:30:20 PM UTC 24 Oct 12 01:33:19 PM UTC 24 12874981836 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_alert_test.3355802709 Oct 12 01:33:18 PM UTC 24 Oct 12 01:33:20 PM UTC 24 97807849 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_noise_filter.2897454122 Oct 12 01:31:44 PM UTC 24 Oct 12 01:33:22 PM UTC 24 150259349218 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/0.uart_fifo_full.423623438 Oct 12 01:29:01 PM UTC 24 Oct 12 01:33:27 PM UTC 24 74743028674 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.219826975 Oct 12 01:32:43 PM UTC 24 Oct 12 01:33:28 PM UTC 24 7758526550 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_noise_filter.1120092215 Oct 12 01:32:31 PM UTC 24 Oct 12 01:33:29 PM UTC 24 63460642859 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_smoke.2838247255 Oct 12 01:33:20 PM UTC 24 Oct 12 01:33:35 PM UTC 24 6168645198 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_rx_oversample.3185990348 Oct 12 01:33:30 PM UTC 24 Oct 12 01:33:36 PM UTC 24 3135747905 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1096466100 Oct 12 01:33:14 PM UTC 24 Oct 12 01:33:36 PM UTC 24 2226174963 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_stress_all.1881873365 Oct 12 01:32:06 PM UTC 24 Oct 12 01:33:39 PM UTC 24 226972302749 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_tx_rx.3605257524 Oct 12 01:32:12 PM UTC 24 Oct 12 01:33:40 PM UTC 24 132945959014 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_intr.2619459614 Oct 12 01:30:13 PM UTC 24 Oct 12 01:33:45 PM UTC 24 263813372323 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.75436432 Oct 12 01:31:14 PM UTC 24 Oct 12 01:33:47 PM UTC 24 215045268340 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.726181477 Oct 12 01:33:37 PM UTC 24 Oct 12 01:33:49 PM UTC 24 3057713378 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.4205804036 Oct 12 01:30:37 PM UTC 24 Oct 12 01:33:49 PM UTC 24 78260626908 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_loopback.2842111681 Oct 12 01:33:09 PM UTC 24 Oct 12 01:33:51 PM UTC 24 10457661580 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_fifo_reset.1715576110 Oct 12 01:29:09 PM UTC 24 Oct 12 01:33:53 PM UTC 24 156697588541 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_alert_test.967466544 Oct 12 01:33:54 PM UTC 24 Oct 12 01:33:56 PM UTC 24 49951217 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_tx_rx.346404411 Oct 12 01:33:21 PM UTC 24 Oct 12 01:33:56 PM UTC 24 35317842160 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.3903527724 Oct 12 01:33:41 PM UTC 24 Oct 12 01:33:58 PM UTC 24 8616510008 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_noise_filter.4170587173 Oct 12 01:32:59 PM UTC 24 Oct 12 01:33:59 PM UTC 24 71964172830 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_fifo_full.329818488 Oct 12 01:33:22 PM UTC 24 Oct 12 01:34:00 PM UTC 24 73445746574 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_stress_all.4193248395 Oct 12 01:33:52 PM UTC 24 Oct 12 01:34:00 PM UTC 24 4259344779 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_smoke.2227834259 Oct 12 01:33:57 PM UTC 24 Oct 12 01:34:00 PM UTC 24 580413084 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_intr.2816882612 Oct 12 01:33:36 PM UTC 24 Oct 12 01:34:05 PM UTC 24 7623541091 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_rx_oversample.4160417464 Oct 12 01:34:00 PM UTC 24 Oct 12 01:34:07 PM UTC 24 1483446893 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.3875802764 Oct 12 01:29:17 PM UTC 24 Oct 12 01:34:08 PM UTC 24 126825279801 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_loopback.2713284366 Oct 12 01:33:46 PM UTC 24 Oct 12 01:34:10 PM UTC 24 9207132095 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.3123908205 Oct 12 01:33:40 PM UTC 24 Oct 12 01:34:13 PM UTC 24 37245624709 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_loopback.3124971017 Oct 12 01:34:14 PM UTC 24 Oct 12 01:34:16 PM UTC 24 152663435 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_noise_filter.2139344855 Oct 12 01:33:37 PM UTC 24 Oct 12 01:34:18 PM UTC 24 12929146266 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.2543034214 Oct 12 01:34:08 PM UTC 24 Oct 12 01:34:19 PM UTC 24 5551160480 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.3186613977 Oct 12 01:34:11 PM UTC 24 Oct 12 01:34:24 PM UTC 24 6862136154 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.1037176408 Oct 12 01:33:51 PM UTC 24 Oct 12 01:34:27 PM UTC 24 5957860823 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_alert_test.3210782153 Oct 12 01:34:29 PM UTC 24 Oct 12 01:34:31 PM UTC 24 37214488 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.3009204485 Oct 12 01:29:14 PM UTC 24 Oct 12 01:34:36 PM UTC 24 166291862721 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3576355995 Oct 12 01:31:38 PM UTC 24 Oct 12 01:34:36 PM UTC 24 149366198646 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_smoke.2362427169 Oct 12 01:34:32 PM UTC 24 Oct 12 01:34:38 PM UTC 24 886295692 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_fifo_full.3728671241 Oct 12 01:31:36 PM UTC 24 Oct 12 01:34:41 PM UTC 24 77587091886 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.90797749 Oct 12 01:35:34 PM UTC 24 Oct 12 01:37:03 PM UTC 24 160128398593 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.2520902582 Oct 12 01:29:28 PM UTC 24 Oct 12 01:34:42 PM UTC 24 92571038414 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_tx_rx.2480325128 Oct 12 01:33:57 PM UTC 24 Oct 12 01:34:46 PM UTC 24 226871845666 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.348269767 Oct 12 01:32:18 PM UTC 24 Oct 12 01:34:54 PM UTC 24 60570155136 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.4095246627 Oct 12 01:34:09 PM UTC 24 Oct 12 01:34:58 PM UTC 24 58709805587 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_rx_oversample.2622092992 Oct 12 01:34:42 PM UTC 24 Oct 12 01:34:59 PM UTC 24 7910227693 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/9.uart_tx_rx.2858196195 Oct 12 01:31:31 PM UTC 24 Oct 12 01:35:00 PM UTC 24 71945499864 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_intr.1074580806 Oct 12 01:32:30 PM UTC 24 Oct 12 01:35:03 PM UTC 24 213164188529 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.3203800595 Oct 12 01:34:19 PM UTC 24 Oct 12 01:35:04 PM UTC 24 1946701121 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.2569047138 Oct 12 01:35:00 PM UTC 24 Oct 12 01:35:07 PM UTC 24 1464639877 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/8.uart_tx_rx.1046963050 Oct 12 01:30:47 PM UTC 24 Oct 12 01:35:09 PM UTC 24 95647310869 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_loopback.2615581505 Oct 12 01:35:05 PM UTC 24 Oct 12 01:35:09 PM UTC 24 3186792877 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.4200885088 Oct 12 01:34:00 PM UTC 24 Oct 12 01:35:13 PM UTC 24 151548479702 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_noise_filter.1207156983 Oct 12 01:34:05 PM UTC 24 Oct 12 01:35:14 PM UTC 24 74827435881 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_fifo_reset.2406898493 Oct 12 01:34:00 PM UTC 24 Oct 12 01:35:14 PM UTC 24 85124556446 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.1974839346 Oct 12 01:35:00 PM UTC 24 Oct 12 01:35:15 PM UTC 24 31926598786 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/4.uart_stress_all.1947339213 Oct 12 01:29:40 PM UTC 24 Oct 12 01:35:15 PM UTC 24 152279086931 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.70918239 Oct 12 01:32:52 PM UTC 24 Oct 12 01:35:15 PM UTC 24 288937647413 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/6.uart_stress_all.3145900777 Oct 12 01:30:24 PM UTC 24 Oct 12 01:35:16 PM UTC 24 424423546752 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.2708255844 Oct 12 01:33:29 PM UTC 24 Oct 12 01:35:16 PM UTC 24 87461209294 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_alert_test.2682570365 Oct 12 01:35:14 PM UTC 24 Oct 12 01:35:16 PM UTC 24 45123449 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_smoke.1695338671 Oct 12 01:35:14 PM UTC 24 Oct 12 01:35:17 PM UTC 24 761343385 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_tx_rx.2741203470 Oct 12 01:32:48 PM UTC 24 Oct 12 01:35:18 PM UTC 24 65959687047 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.2378229274 Oct 12 01:30:41 PM UTC 24 Oct 12 01:35:18 PM UTC 24 219274259533 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_intr.3238864230 Oct 12 01:34:01 PM UTC 24 Oct 12 01:35:21 PM UTC 24 22994528713 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_fifo_full.2990672372 Oct 12 01:34:38 PM UTC 24 Oct 12 01:35:21 PM UTC 24 80126992041 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_intr.2795502667 Oct 12 01:35:17 PM UTC 24 Oct 12 01:35:22 PM UTC 24 15959326758 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.1792603411 Oct 12 01:35:19 PM UTC 24 Oct 12 01:35:25 PM UTC 24 779882087 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_stress_all.224091557 Oct 12 01:32:43 PM UTC 24 Oct 12 01:35:28 PM UTC 24 184747591143 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_noise_filter.3285263985 Oct 12 01:35:17 PM UTC 24 Oct 12 01:35:30 PM UTC 24 27515042662 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_noise_filter.1842965682 Oct 12 01:34:54 PM UTC 24 Oct 12 01:35:31 PM UTC 24 45008529570 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_alert_test.396663488 Oct 12 01:35:29 PM UTC 24 Oct 12 01:35:31 PM UTC 24 13986395 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/11.uart_fifo_full.3775452206 Oct 12 01:32:48 PM UTC 24 Oct 12 01:35:32 PM UTC 24 227056565380 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/13.uart_perf.1542400979 Oct 12 01:34:17 PM UTC 24 Oct 12 01:35:32 PM UTC 24 5334172285 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.2782618308 Oct 12 01:35:19 PM UTC 24 Oct 12 01:35:36 PM UTC 24 3392855174 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.3369834547 Oct 12 01:32:32 PM UTC 24 Oct 12 01:35:36 PM UTC 24 164535528482 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_loopback.4114401502 Oct 12 01:35:19 PM UTC 24 Oct 12 01:35:37 PM UTC 24 13945174038 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_smoke.1349216960 Oct 12 01:35:32 PM UTC 24 Oct 12 01:35:37 PM UTC 24 555718034 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_fifo_reset.3742636726 Oct 12 01:35:16 PM UTC 24 Oct 12 01:35:38 PM UTC 24 172017476209 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.2012927368 Oct 12 01:35:19 PM UTC 24 Oct 12 01:35:38 PM UTC 24 14399537254 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3827111402 Oct 12 01:35:38 PM UTC 24 Oct 12 01:35:41 PM UTC 24 918054517 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.1049266118 Oct 12 01:35:40 PM UTC 24 Oct 12 01:35:44 PM UTC 24 7458388746 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_rx_oversample.1983560837 Oct 12 01:35:38 PM UTC 24 Oct 12 01:35:46 PM UTC 24 2667488913 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_fifo_full.2649154381 Oct 12 01:35:34 PM UTC 24 Oct 12 01:35:47 PM UTC 24 15705432208 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_fifo_reset.4041003601 Oct 12 01:35:34 PM UTC 24 Oct 12 01:35:50 PM UTC 24 8552149996 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_rx_oversample.764431778 Oct 12 01:35:17 PM UTC 24 Oct 12 01:36:04 PM UTC 24 7279873683 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_alert_test.2391085916 Oct 12 01:36:02 PM UTC 24 Oct 12 01:36:04 PM UTC 24 22469487 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_intr.3173461082 Oct 12 01:34:48 PM UTC 24 Oct 12 01:36:04 PM UTC 24 18955706046 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.2145300805 Oct 12 01:35:10 PM UTC 24 Oct 12 01:36:08 PM UTC 24 9067490173 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_smoke.423087753 Oct 12 01:36:04 PM UTC 24 Oct 12 01:36:08 PM UTC 24 539829988 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_tx_rx.2909077230 Oct 12 01:35:32 PM UTC 24 Oct 12 01:36:10 PM UTC 24 22220889242 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_loopback.2027043629 Oct 12 01:35:42 PM UTC 24 Oct 12 01:36:11 PM UTC 24 9559538241 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.4119877594 Oct 12 01:35:49 PM UTC 24 Oct 12 01:36:12 PM UTC 24 1668748417 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.3119033959 Oct 12 01:35:16 PM UTC 24 Oct 12 01:36:17 PM UTC 24 94792513925 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/16.uart_noise_filter.2930245729 Oct 12 01:35:38 PM UTC 24 Oct 12 01:36:22 PM UTC 24 21560225062 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_fifo_full.1187678760 Oct 12 01:36:05 PM UTC 24 Oct 12 01:36:25 PM UTC 24 21565410260 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.577445292 Oct 12 01:36:18 PM UTC 24 Oct 12 01:36:26 PM UTC 24 3524018239 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/coverage/default/1.uart_perf.498893301 Oct 12 01:29:09 PM UTC 24 Oct 12 01:36:27 PM UTC 24 8431796975 ps
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