Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2608

1

T1

1

T2

1

T3

1

auto[UartRx]

2608

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4539	1			T1	2		T2	2		T3	2
values[1]	46	1			T38	1		T42	1		T402	2
values[2]	56	1			T32	1		T23	2		T41	1
values[3]	39	1			T34	1		T39	1		T40	1
values[4]	62	1			T34	1		T39	1		T41	1
values[5]	62	1			T41	2		T43	1		T92	1
values[6]	57	1			T33	1		T23	2		T40	1
values[7]	56	1			T33	1		T34	1		T39	1
values[8]	65	1			T32	1		T33	1		T34	2
values[9]	85	1			T39	1		T41	2		T42	2
values[10]	104	1			T32	1		T33	1		T23	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2373	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	11	1			T38	1		T42	1		T94	1
auto[UartTx]	values[2]	23	1			T32	1		T23	1		T41	1
auto[UartTx]	values[3]	13	1			T40	1		T407	1		T93	1
auto[UartTx]	values[4]	25	1			T39	1		T41	1		T402	1
auto[UartTx]	values[5]	27	1			T368	1		T121	1		T408	2
auto[UartTx]	values[6]	18	1			T23	1		T40	1		T43	1
auto[UartTx]	values[7]	20	1			T33	1		T42	1		T43	2
auto[UartTx]	values[8]	24	1			T33	1		T34	2		T38	1
auto[UartTx]	values[9]	24	1			T42	1		T43	1		T165	1
auto[UartTx]	values[10]	36	1			T23	1		T39	1		T407	2
auto[UartRx]	values[0]	2166	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	35	1			T402	2		T120	1		T122	1
auto[UartRx]	values[2]	33	1			T23	1		T43	1		T93	2
auto[UartRx]	values[3]	26	1			T34	1		T39	1		T43	1
auto[UartRx]	values[4]	37	1			T34	1		T42	1		T121	1
auto[UartRx]	values[5]	35	1			T41	2		T43	1		T92	1
auto[UartRx]	values[6]	39	1			T33	1		T23	1		T41	1
auto[UartRx]	values[7]	36	1			T34	1		T39	1		T41	1
auto[UartRx]	values[8]	41	1			T32	1		T40	1		T42	1
auto[UartRx]	values[9]	61	1			T39	1		T41	2		T42	1
auto[UartRx]	values[10]	68	1			T32	1		T33	1		T23	1