Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1898	1			T1	8		T11	1		T13	3
auto[BaudRate115200]	1571	1			T2	1		T3	1		T10	1
auto[BaudRate230400]	1537	1			T2	1		T6	3		T11	2
auto[BaudRate128Kbps]	1502	1			T13	9		T29	1		T18	1
auto[BaudRate256Kbps]	1765	1			T2	1		T11	1		T13	9
auto[BaudRate1Mbps]	1374	1			T2	1		T7	1		T11	3
auto[BaudRate1p5Mbps]	1074	1			T2	3		T3	1		T7	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1070	1			T16	2		T12	8		T340	1
freqs[25]	1057	1			T2	7		T6	3		T25	2
freqs[48]	500	1			T48	7		T110	10		T293	8
freqs[50]	422	1			T3	2		T17	1		T367	2
freqs[100]	917	1			T32	7		T130	5		T327	2

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	206	1			T16	2		T28	8		T125	2
auto[BaudRate9600]	freqs[25]	210	1			T34	6		T112	3		T190	1
auto[BaudRate9600]	freqs[48]	104	1			T48	1		T409	19		T155	2
auto[BaudRate9600]	freqs[50]	62	1			T367	2		T55	3		T133	1
auto[BaudRate9600]	freqs[100]	152	1			T39	2		T98	20		T285	1
auto[BaudRate115200]	freqs[24]	155	1			T12	1		T35	6		T28	3
auto[BaudRate115200]	freqs[25]	154	1			T2	1		T25	1		T34	3
auto[BaudRate115200]	freqs[48]	57	1			T357	1		T113	1		T410	3
auto[BaudRate115200]	freqs[50]	80	1			T3	1		T17	1		T411	3
auto[BaudRate115200]	freqs[100]	126	1			T32	2		T130	1		T39	5
auto[BaudRate230400]	freqs[24]	157	1			T12	2		T35	1		T387	1
auto[BaudRate230400]	freqs[25]	145	1			T2	1		T6	3		T25	1
auto[BaudRate230400]	freqs[48]	62	1			T48	2		T110	1		T78	1
auto[BaudRate230400]	freqs[50]	61	1			T411	6		T133	1		T140	2
auto[BaudRate230400]	freqs[100]	135	1			T32	1		T130	1		T39	2
auto[BaudRate128Kbps]	freqs[24]	170	1			T35	4		T20	1		T28	6
auto[BaudRate128Kbps]	freqs[25]	146	1			T112	1		T190	1		T321	2
auto[BaudRate128Kbps]	freqs[48]	49	1			T48	1		T110	1		T113	1
auto[BaudRate128Kbps]	freqs[50]	54	1			T140	1		T147	1		T141	1
auto[BaudRate128Kbps]	freqs[100]	105	1			T32	1		T327	1		T39	2
auto[BaudRate256Kbps]	freqs[24]	176	1			T12	3		T340	1		T35	1
auto[BaudRate256Kbps]	freqs[25]	170	1			T2	1		T34	1		T112	1
auto[BaudRate256Kbps]	freqs[48]	68	1			T48	1		T110	4		T353	2
auto[BaudRate256Kbps]	freqs[50]	60	1			T325	1		T411	3		T133	2
auto[BaudRate256Kbps]	freqs[100]	141	1			T32	1		T345	1		T341	1
auto[BaudRate1Mbps]	freqs[24]	127	1			T35	4		T28	3		T125	2
auto[BaudRate1Mbps]	freqs[25]	149	1			T2	1		T34	6		T299	3
auto[BaudRate1Mbps]	freqs[48]	94	1			T48	1		T110	3		T293	7
auto[BaudRate1Mbps]	freqs[50]	44	1			T43	4		T141	1		T376	2
auto[BaudRate1Mbps]	freqs[100]	114	1			T32	1		T130	1		T39	1
auto[BaudRate1p5Mbps]	freqs[25]	83	1			T2	3		T112	2		T299	1
auto[BaudRate1p5Mbps]	freqs[48]	66	1			T48	1		T110	1		T293	1
auto[BaudRate1p5Mbps]	freqs[50]	61	1			T3	1		T325	1		T133	2
auto[BaudRate1p5Mbps]	freqs[100]	144	1			T32	1		T130	2		T327	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded