Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.45	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	7	123	94.62

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	7	123	94.62	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	26209285	1			T1	1		T2	19		T6	1
all_levels[1]	147252	1			T11	1		T17	3		T12	1
all_levels[2]	1997	1			T32	1		T35	3		T48	1
all_levels[3]	925	1			T19	2		T35	4		T33	1
all_levels[4]	604	1			T17	2		T12	1		T33	3
all_levels[5]	436	1			T2	1		T35	2		T125	1
all_levels[6]	370	1			T2	1		T11	2		T19	1
all_levels[7]	298	1			T35	2		T125	1		T126	1
all_levels[8]	257	1			T11	2		T19	3		T35	2
all_levels[9]	199	1			T110	1		T109	1		T31	2
all_levels[10]	179	1			T51	1		T127	1		T128	1
all_levels[11]	164	1			T2	1		T35	1		T126	3
all_levels[12]	119	1			T110	2		T109	1		T127	1
all_levels[13]	116	1			T31	3		T51	1		T127	1
all_levels[14]	104	1			T12	1		T126	1		T127	1
all_levels[15]	106	1			T35	1		T109	2		T127	1
all_levels[16]	68	1			T110	1		T109	1		T129	1
all_levels[17]	105	1			T130	1		T31	1		T127	1
all_levels[18]	76	1			T2	1		T12	1		T109	1
all_levels[19]	52	1			T109	1		T129	1		T131	1
all_levels[20]	73	1			T19	3		T109	1		T31	1
all_levels[21]	42	1			T110	1		T132	1		T133	2
all_levels[22]	55	1			T12	1		T126	1		T131	1
all_levels[23]	54	1			T2	1		T111	1		T102	2
all_levels[24]	45	1			T134	1		T135	2		T136	1
all_levels[25]	25	1			T130	1		T137	1		T138	1
all_levels[26]	38	1			T19	1		T134	1		T139	1
all_levels[27]	50	1			T126	2		T114	1		T140	1
all_levels[28]	43	1			T110	1		T109	1		T141	1
all_levels[29]	40	1			T2	1		T109	1		T107	1
all_levels[30]	31	1			T131	1		T142	1		T143	1
all_levels[31]	23	1			T107	1		T144	1		T145	1
all_levels[32]	23	1			T110	1		T111	1		T146	1
all_levels[33]	25	1			T110	1		T50	1		T147	1
all_levels[34]	12	1			T2	1		T144	1		T148	1
all_levels[35]	23	1			T149	2		T150	1		T151	1
all_levels[36]	22	1			T2	1		T110	1		T136	1
all_levels[37]	26	1			T110	3		T152	1		T153	1
all_levels[38]	16	1			T111	1		T154	1		T155	1
all_levels[39]	23	1			T138	1		T152	1		T134	2
all_levels[40]	14	1			T130	1		T153	1		T156	1
all_levels[41]	14	1			T137	1		T157	1		T158	1
all_levels[42]	32	1			T12	1		T114	1		T152	2
all_levels[43]	13	1			T159	1		T160	1		T161	1
all_levels[44]	16	1			T134	1		T156	1		T136	1
all_levels[45]	16	1			T134	1		T159	2		T162	1
all_levels[46]	12	1			T163	1		T156	2		T162	1
all_levels[47]	13	1			T50	1		T132	1		T114	1
all_levels[48]	13	1			T114	1		T143	1		T164	1
all_levels[49]	10	1			T19	1		T142	1		T165	1
all_levels[50]	20	1			T126	1		T166	1		T167	1
all_levels[51]	9	1			T168	1		T169	1		T170	1
all_levels[52]	17	1			T126	4		T171	1		T172	1
all_levels[53]	14	1			T130	1		T129	1		T166	1
all_levels[54]	8	1			T152	1		T173	1		T139	1
all_levels[55]	17	1			T174	2		T175	1		T154	1
all_levels[56]	6	1			T176	1		T159	2		T177	2
all_levels[57]	10	1			T11	2		T136	1		T178	4
all_levels[58]	8	1			T126	1		T132	1		T134	1
all_levels[59]	12	1			T179	1		T180	1		T181	1
all_levels[60]	8	1			T114	1		T148	1		T182	3
all_levels[61]	8	1			T183	2		T180	1		T184	1
all_levels[62]	4	1			T173	1		T185	1		T186	2
all_levels[63]	6	1			T187	1		T188	1		T189	3
all_levels[64]	64	1			T2	2		T111	1		T31	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26360070

1

T2

29

T11

13

T17

16

auto[1]

3695

1

T1

1

T6

1

T11

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	7	123	94.62	7

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[21]]	[auto[1]]	0	1	1
[all_levels[32]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[40] , all_levels[41]]	[auto[1]]	--	--	2
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	26206025	1			T2	19		T11	9		T17	11
all_levels[0]	auto[1]	3260	1			T1	1		T6	1		T11	2
all_levels[1]	auto[0]	147163	1			T11	1		T17	3		T12	1
all_levels[1]	auto[1]	89	1			T19	1		T190	1		T191	1
all_levels[2]	auto[0]	1974	1			T32	1		T35	3		T48	1
all_levels[2]	auto[1]	23	1			T190	1		T192	2		T193	1
all_levels[3]	auto[0]	904	1			T19	2		T35	4		T33	1
all_levels[3]	auto[1]	21	1			T194	5		T195	2		T196	2
all_levels[4]	auto[0]	588	1			T17	2		T12	1		T33	3
all_levels[4]	auto[1]	16	1			T163	1		T133	1		T170	1
all_levels[5]	auto[0]	428	1			T2	1		T35	2		T125	1
all_levels[5]	auto[1]	8	1			T193	2		T123	1		T197	1
all_levels[6]	auto[0]	342	1			T2	1		T11	1		T19	1
all_levels[6]	auto[1]	28	1			T11	1		T34	1		T198	2
all_levels[7]	auto[0]	291	1			T35	2		T125	1		T126	1
all_levels[7]	auto[1]	7	1			T199	1		T200	1		T201	1
all_levels[8]	auto[0]	249	1			T11	1		T19	2		T35	2
all_levels[8]	auto[1]	8	1			T11	1		T19	1		T163	1
all_levels[9]	auto[0]	190	1			T110	1		T109	1		T31	2
all_levels[9]	auto[1]	9	1			T202	2		T203	1		T204	3
all_levels[10]	auto[0]	168	1			T51	1		T127	1		T128	1
all_levels[10]	auto[1]	11	1			T205	1		T206	2		T207	1
all_levels[11]	auto[0]	153	1			T2	1		T35	1		T126	1
all_levels[11]	auto[1]	11	1			T126	2		T194	1		T208	3
all_levels[12]	auto[0]	114	1			T110	2		T109	1		T127	1
all_levels[12]	auto[1]	5	1			T209	1		T210	1		T211	1
all_levels[13]	auto[0]	107	1			T31	3		T51	1		T127	1
all_levels[13]	auto[1]	9	1			T192	1		T146	1		T212	4
all_levels[14]	auto[0]	98	1			T12	1		T126	1		T127	1
all_levels[14]	auto[1]	6	1			T198	1		T213	1		T214	1
all_levels[15]	auto[0]	100	1			T35	1		T109	2		T127	1
all_levels[15]	auto[1]	6	1			T215	1		T216	1		T217	3
all_levels[16]	auto[0]	65	1			T110	1		T109	1		T129	1
all_levels[16]	auto[1]	3	1			T218	1		T219	1		T220	1
all_levels[17]	auto[0]	89	1			T130	1		T31	1		T127	1
all_levels[17]	auto[1]	16	1			T221	1		T222	1		T203	1
all_levels[18]	auto[0]	66	1			T2	1		T12	1		T109	1
all_levels[18]	auto[1]	10	1			T223	1		T224	1		T225	2
all_levels[19]	auto[0]	49	1			T109	1		T129	1		T131	1
all_levels[19]	auto[1]	3	1			T133	2		T226	1		-	-
all_levels[20]	auto[0]	64	1			T19	1		T109	1		T31	1
all_levels[20]	auto[1]	9	1			T19	2		T227	1		T210	1
all_levels[21]	auto[0]	42	1			T110	1		T132	1		T133	2
all_levels[22]	auto[0]	50	1			T12	1		T126	1		T131	1
all_levels[22]	auto[1]	5	1			T178	1		T228	1		T229	1
all_levels[23]	auto[0]	46	1			T2	1		T111	1		T102	2
all_levels[23]	auto[1]	8	1			T172	2		T189	1		T230	2
all_levels[24]	auto[0]	38	1			T134	1		T135	2		T136	1
all_levels[24]	auto[1]	7	1			T231	1		T232	2		T233	3
all_levels[25]	auto[0]	23	1			T130	1		T137	1		T138	1
all_levels[25]	auto[1]	2	1			T234	2		-	-		-	-
all_levels[26]	auto[0]	32	1			T19	1		T134	1		T139	1
all_levels[26]	auto[1]	6	1			T235	2		T201	3		T236	1
all_levels[27]	auto[0]	43	1			T126	1		T114	1		T140	1
all_levels[27]	auto[1]	7	1			T126	1		T152	1		T237	3
all_levels[28]	auto[0]	38	1			T110	1		T109	1		T141	1
all_levels[28]	auto[1]	5	1			T238	2		T239	1		T240	1
all_levels[29]	auto[0]	37	1			T2	1		T109	1		T107	1
all_levels[29]	auto[1]	3	1			T209	1		T241	1		T242	1
all_levels[30]	auto[0]	28	1			T131	1		T142	1		T143	1
all_levels[30]	auto[1]	3	1			T243	2		T244	1		-	-
all_levels[31]	auto[0]	22	1			T107	1		T144	1		T145	1
all_levels[31]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[32]	auto[0]	23	1			T110	1		T111	1		T146	1
all_levels[33]	auto[0]	22	1			T110	1		T50	1		T147	1
all_levels[33]	auto[1]	3	1			T246	1		T247	1		T228	1
all_levels[34]	auto[0]	11	1			T2	1		T144	1		T148	1
all_levels[34]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[35]	auto[0]	23	1			T149	2		T150	1		T151	1
all_levels[36]	auto[0]	20	1			T2	1		T110	1		T136	1
all_levels[36]	auto[1]	2	1			T222	1		T248	1		-	-
all_levels[37]	auto[0]	24	1			T110	3		T152	1		T153	1
all_levels[37]	auto[1]	2	1			T249	1		T250	1		-	-
all_levels[38]	auto[0]	15	1			T111	1		T154	1		T155	1
all_levels[38]	auto[1]	1	1			T251	1		-	-		-	-
all_levels[39]	auto[0]	20	1			T138	1		T152	1		T134	2
all_levels[39]	auto[1]	3	1			T252	1		T233	1		T253	1
all_levels[40]	auto[0]	14	1			T130	1		T153	1		T156	1
all_levels[41]	auto[0]	14	1			T137	1		T157	1		T158	1
all_levels[42]	auto[0]	22	1			T12	1		T114	1		T152	1
all_levels[42]	auto[1]	10	1			T152	1		T198	1		T254	3
all_levels[43]	auto[0]	11	1			T159	1		T160	1		T161	1
all_levels[43]	auto[1]	2	1			T255	2		-	-		-	-
all_levels[44]	auto[0]	12	1			T134	1		T156	1		T136	1
all_levels[44]	auto[1]	4	1			T178	1		T256	1		T257	1
all_levels[45]	auto[0]	10	1			T134	1		T159	1		T162	1
all_levels[45]	auto[1]	6	1			T159	1		T211	1		T258	4
all_levels[46]	auto[0]	10	1			T163	1		T156	2		T162	1
all_levels[46]	auto[1]	2	1			T219	1		T253	1		-	-
all_levels[47]	auto[0]	13	1			T50	1		T132	1		T114	1
all_levels[48]	auto[0]	11	1			T114	1		T143	1		T164	1
all_levels[48]	auto[1]	2	1			T259	2		-	-		-	-
all_levels[49]	auto[0]	8	1			T19	1		T142	1		T165	1
all_levels[49]	auto[1]	2	1			T260	1		T226	1		-	-
all_levels[50]	auto[0]	15	1			T126	1		T166	1		T167	1
all_levels[50]	auto[1]	5	1			T261	1		T262	2		T263	2
all_levels[51]	auto[0]	8	1			T168	1		T169	1		T170	1
all_levels[51]	auto[1]	1	1			T264	1		-	-		-	-
all_levels[52]	auto[0]	10	1			T126	2		T171	1		T172	1
all_levels[52]	auto[1]	7	1			T126	2		T265	2		T266	2
all_levels[53]	auto[0]	13	1			T130	1		T129	1		T166	1
all_levels[53]	auto[1]	1	1			T267	1		-	-		-	-
all_levels[54]	auto[0]	7	1			T152	1		T173	1		T139	1
all_levels[54]	auto[1]	1	1			T268	1		-	-		-	-
all_levels[55]	auto[0]	12	1			T174	1		T175	1		T154	1
all_levels[55]	auto[1]	5	1			T174	1		T263	1		T269	3
all_levels[56]	auto[0]	4	1			T176	1		T159	1		T177	1
all_levels[56]	auto[1]	2	1			T159	1		T177	1		-	-
all_levels[57]	auto[0]	5	1			T11	1		T136	1		T178	1
all_levels[57]	auto[1]	5	1			T11	1		T178	3		T266	1
all_levels[58]	auto[0]	8	1			T126	1		T132	1		T134	1
all_levels[59]	auto[0]	8	1			T179	1		T180	1		T181	1
all_levels[59]	auto[1]	4	1			T270	3		T271	1		-	-
all_levels[60]	auto[0]	5	1			T114	1		T148	1		T182	1
all_levels[60]	auto[1]	3	1			T182	2		T272	1		-	-
all_levels[61]	auto[0]	6	1			T183	1		T180	1		T184	1
all_levels[61]	auto[1]	2	1			T183	1		T273	1		-	-
all_levels[62]	auto[0]	3	1			T173	1		T185	1		T186	1
all_levels[62]	auto[1]	1	1			T186	1		-	-		-	-
all_levels[63]	auto[0]	4	1			T187	1		T188	1		T189	1
all_levels[63]	auto[1]	2	1			T189	2		-	-		-	-
all_levels[64]	auto[0]	53	1			T2	2		T111	1		T31	1
all_levels[64]	auto[1]	11	1			T274	1		T275	1		T236	1