Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	91797	1			T1	1		T2	26		T3	2
all_pins[1]	91797	1			T1	1		T2	26		T3	2
all_pins[2]	91797	1			T1	1		T2	26		T3	2
all_pins[3]	91797	1			T1	1		T2	26		T3	2
all_pins[4]	91797	1			T1	1		T2	26		T3	2
all_pins[5]	91797	1			T1	1		T2	26		T3	2
all_pins[6]	91797	1			T1	1		T2	26		T3	2
all_pins[7]	91797	1			T1	1		T2	26		T3	2
all_pins[8]	91797	1			T1	1		T2	26		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	786911	1			T1	8		T2	217		T3	18
values[0x1]	39262	1			T1	1		T2	17		T6	2
transitions[0x0=>0x1]	30765	1			T1	1		T2	16		T6	1
transitions[0x1=>0x0]	30562	1			T2	15		T6	1		T11	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	72484	1			T2	24		T3	2		T7	2
all_pins[0]	values[0x1]	19313	1			T1	1		T2	2		T6	1
all_pins[0]	transitions[0x0=>0x1]	18895	1			T1	1		T2	2		T6	1
all_pins[0]	transitions[0x1=>0x0]	732	1			T2	12		T21	8		T22	6
all_pins[1]	values[0x0]	90647	1			T1	1		T2	14		T3	2
all_pins[1]	values[0x1]	1150	1			T2	12		T21	8		T32	2
all_pins[1]	transitions[0x0=>0x1]	1049	1			T2	12		T21	8		T32	2
all_pins[1]	transitions[0x1=>0x0]	1930	1			T2	1		T11	1		T17	1
all_pins[2]	values[0x0]	89766	1			T1	1		T2	25		T3	2
all_pins[2]	values[0x1]	2031	1			T2	1		T11	1		T17	1
all_pins[2]	transitions[0x0=>0x1]	1980	1			T2	1		T11	1		T17	1
all_pins[2]	transitions[0x1=>0x0]	207	1			T19	1		T276	1		T76	2
all_pins[3]	values[0x0]	91539	1			T1	1		T2	26		T3	2
all_pins[3]	values[0x1]	258	1			T19	1		T276	1		T76	2
all_pins[3]	transitions[0x0=>0x1]	227	1			T19	1		T276	1		T76	2
all_pins[3]	transitions[0x1=>0x0]	305	1			T21	5		T22	9		T23	2
all_pins[4]	values[0x0]	91461	1			T1	1		T2	26		T3	2
all_pins[4]	values[0x1]	336	1			T21	5		T22	9		T23	2
all_pins[4]	transitions[0x0=>0x1]	280	1			T21	4		T22	7		T23	2
all_pins[4]	transitions[0x1=>0x0]	138	1			T38	2		T276	1		T278	1
all_pins[5]	values[0x0]	91603	1			T1	1		T2	26		T3	2
all_pins[5]	values[0x1]	194	1			T21	1		T22	2		T38	4
all_pins[5]	transitions[0x0=>0x1]	150	1			T21	1		T22	2		T38	2
all_pins[5]	transitions[0x1=>0x0]	719	1			T19	1		T111	1		T125	4
all_pins[6]	values[0x0]	91034	1			T1	1		T2	26		T3	2
all_pins[6]	values[0x1]	763	1			T19	1		T111	1		T125	4
all_pins[6]	transitions[0x0=>0x1]	707	1			T19	1		T111	1		T125	4
all_pins[6]	transitions[0x1=>0x0]	225	1			T21	4		T107	2		T277	1
all_pins[7]	values[0x0]	91516	1			T1	1		T2	26		T3	2
all_pins[7]	values[0x1]	281	1			T21	4		T107	2		T277	1
all_pins[7]	transitions[0x0=>0x1]	150	1			T21	4		T277	1		T142	3
all_pins[7]	transitions[0x1=>0x0]	14805	1			T2	2		T6	1		T29	19
all_pins[8]	values[0x0]	76861	1			T1	1		T2	24		T3	2
all_pins[8]	values[0x1]	14936	1			T2	2		T6	1		T29	19
all_pins[8]	transitions[0x0=>0x1]	7327	1			T2	1		T29	18		T12	6
all_pins[8]	transitions[0x1=>0x0]	11501	1			T11	1		T32	4		T35	1