Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7575193	1			T2	11		T11	9		T29	9
all_levels[1]	1350187	1			T2	2		T17	5		T12	2
all_levels[2]	468818	1			T12	1		T19	1		T35	8
all_levels[3]	241289	1			T35	3		T33	2		T48	2
all_levels[4]	201873	1			T12	2		T35	1		T33	2
all_levels[5]	284332	1			T19	1		T35	5		T33	2
all_levels[6]	191378	1			T35	3		T33	2		T125	4
all_levels[7]	163764	1			T35	1		T33	2		T125	23
all_levels[8]	398787	1			T33	2		T125	10		T23	148
all_levels[9]	162174	1			T32	9		T35	1		T33	2
all_levels[10]	185663	1			T33	2		T48	4		T125	9
all_levels[11]	158234	1			T33	591		T48	1		T125	4
all_levels[12]	193745	1			T33	2336		T110	1		T23	81
all_levels[13]	183262	1			T35	3		T33	1477		T110	1
all_levels[14]	160313	1			T35	20		T33	1463		T125	3
all_levels[15]	250783	1			T33	2332		T48	1		T110	2
all_levels[16]	203819	1			T33	1908		T48	2		T125	1
all_levels[17]	351277	1			T35	2		T33	1631		T386	7
all_levels[18]	161769	1			T35	7		T33	2339		T130	3
all_levels[19]	172731	1			T35	12		T33	1809		T48	3
all_levels[20]	298105	1			T35	1		T48	1		T23	101
all_levels[21]	168165	1			T110	4		T297	4		T23	167
all_levels[22]	206228	1			T35	2		T23	292		T288	11
all_levels[23]	149319	1			T23	315		T288	1		T52	109
all_levels[24]	138519	1			T11	3		T23	314		T52	108
all_levels[25]	322391	1			T12	2		T48	9		T110	1
all_levels[26]	133569	1			T35	2		T125	1		T23	325
all_levels[27]	137250	1			T109	1		T23	315		T52	108
all_levels[28]	132946	1			T35	2		T126	3		T23	315
all_levels[29]	242757	1			T110	2		T125	86		T109	1
all_levels[30]	284252	1			T2	2		T48	2		T110	3
all_levels[31]	346677	1			T2	3		T35	13		T48	3
all_levels[32]	10744010	1			T2	11		T11	8		T12	9

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26360070

1

T2

29

T11

13

T17

16

auto[1]

3509

1

T11

7

T29

9

T15

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7573215	1			T2	11		T11	6		T17	11
all_levels[0]	auto[1]	1978	1			T11	3		T29	9		T15	1
all_levels[1]	auto[0]	1349961	1			T2	2		T17	5		T12	2
all_levels[1]	auto[1]	226	1			T19	1		T110	1		T131	1
all_levels[2]	auto[0]	468788	1			T12	1		T19	1		T35	8
all_levels[2]	auto[1]	30	1			T198	1		T156	1		T397	1
all_levels[3]	auto[0]	241203	1			T35	3		T33	2		T48	2
all_levels[3]	auto[1]	86	1			T387	5		T22	16		T99	1
all_levels[4]	auto[0]	201841	1			T12	2		T35	1		T33	2
all_levels[4]	auto[1]	32	1			T34	1		T413	1		T414	1
all_levels[5]	auto[0]	284311	1			T19	1		T35	5		T33	2
all_levels[5]	auto[1]	21	1			T152	1		T401	1		T150	2
all_levels[6]	auto[0]	191362	1			T35	3		T33	2		T125	4
all_levels[6]	auto[1]	16	1			T191	1		T415	1		T416	1
all_levels[7]	auto[0]	163670	1			T35	1		T33	2		T125	22
all_levels[7]	auto[1]	94	1			T125	1		T166	1		T106	27
all_levels[8]	auto[0]	398757	1			T33	2		T125	10		T23	148
all_levels[8]	auto[1]	30	1			T192	1		T202	1		T417	1
all_levels[9]	auto[0]	162159	1			T32	9		T35	1		T33	2
all_levels[9]	auto[1]	15	1			T145	1		T199	1		T418	1
all_levels[10]	auto[0]	185640	1			T33	2		T48	4		T125	9
all_levels[10]	auto[1]	23	1			T304	1		T190	1		T170	1
all_levels[11]	auto[0]	158203	1			T33	591		T48	1		T125	4
all_levels[11]	auto[1]	31	1			T130	1		T138	1		T152	1
all_levels[12]	auto[0]	193722	1			T33	2336		T110	1		T23	81
all_levels[12]	auto[1]	23	1			T100	1		T198	1		T289	1
all_levels[13]	auto[0]	183240	1			T35	2		T33	1477		T110	1
all_levels[13]	auto[1]	22	1			T35	1		T163	1		T400	1
all_levels[14]	auto[0]	160290	1			T35	20		T33	1463		T125	3
all_levels[14]	auto[1]	23	1			T419	1		T231	3		T420	2
all_levels[15]	auto[0]	250636	1			T33	2332		T48	1		T110	2
all_levels[15]	auto[1]	147	1			T342	1		T104	4		T295	1
all_levels[16]	auto[0]	203807	1			T33	1908		T48	2		T125	1
all_levels[16]	auto[1]	12	1			T150	1		T421	1		T422	2
all_levels[17]	auto[0]	351259	1			T35	2		T33	1631		T386	6
all_levels[17]	auto[1]	18	1			T386	1		T53	1		T104	1
all_levels[18]	auto[0]	161753	1			T35	7		T33	2339		T130	2
all_levels[18]	auto[1]	16	1			T130	1		T322	1		T355	1
all_levels[19]	auto[0]	172716	1			T35	12		T33	1809		T48	3
all_levels[19]	auto[1]	15	1			T78	1		T423	1		T424	1
all_levels[20]	auto[0]	298085	1			T35	1		T48	1		T23	101
all_levels[20]	auto[1]	20	1			T425	1		T426	2		T170	1
all_levels[21]	auto[0]	168151	1			T110	4		T297	4		T23	167
all_levels[21]	auto[1]	14	1			T149	1		T194	1		T427	1
all_levels[22]	auto[0]	206209	1			T35	2		T23	292		T288	11
all_levels[22]	auto[1]	19	1			T428	1		T429	1		T222	1
all_levels[23]	auto[0]	149298	1			T23	315		T288	1		T52	109
all_levels[23]	auto[1]	21	1			T291	1		T384	1		T183	1
all_levels[24]	auto[0]	138509	1			T11	2		T23	314		T52	108
all_levels[24]	auto[1]	10	1			T11	1		T319	1		T430	1
all_levels[25]	auto[0]	322367	1			T12	2		T48	9		T110	1
all_levels[25]	auto[1]	24	1			T102	1		T431	2		T151	1
all_levels[26]	auto[0]	133563	1			T35	2		T125	1		T23	325
all_levels[26]	auto[1]	6	1			T40	1		T432	1		T433	1
all_levels[27]	auto[0]	137231	1			T109	1		T23	315		T52	108
all_levels[27]	auto[1]	19	1			T304	1		T434	1		T274	3
all_levels[28]	auto[0]	132929	1			T35	2		T126	1		T23	315
all_levels[28]	auto[1]	17	1			T126	2		T294	1		T187	1
all_levels[29]	auto[0]	242744	1			T110	2		T125	86		T109	1
all_levels[29]	auto[1]	13	1			T192	1		T435	1		T161	1
all_levels[30]	auto[0]	284239	1			T2	2		T48	2		T110	3
all_levels[30]	auto[1]	13	1			T370	1		T119	1		T193	2
all_levels[31]	auto[0]	346659	1			T2	3		T35	13		T48	3
all_levels[31]	auto[1]	18	1			T109	1		T154	1		T436	1
all_levels[32]	auto[0]	10743553	1			T2	11		T11	5		T12	9
all_levels[32]	auto[1]	457	1			T11	3		T19	4		T126	5