Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	696	1			T23	4		T38	11		T76	4
all_values[1]	696	1			T23	4		T38	11		T76	4
all_values[2]	696	1			T23	4		T38	11		T76	4
all_values[3]	696	1			T23	4		T38	11		T76	4
all_values[4]	696	1			T23	4		T38	11		T76	4
all_values[5]	696	1			T23	4		T38	11		T76	4
all_values[6]	696	1			T23	4		T38	11		T76	4
all_values[7]	696	1			T23	4		T38	11		T76	4
all_values[8]	696	1			T23	4		T38	11		T76	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3357

1

T23

22

T38

57

T76

13

auto[1]

2907

1

T23

14

T38

42

T76

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1945

1

T23

15

T38

29

T76

19

auto[1]

4319

1

T23

21

T38

70

T76

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3623

1

T23

25

T38

56

T76

26

auto[1]

2641

1

T23

11

T38

43

T76

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	232	1			T38	3		T76	2		T77	1
all_values[0]	auto[0]	auto[1]	auto[1]	177	1			T23	3		T38	3		T76	1
all_values[0]	auto[1]	auto[0]	auto[1]	173	1			T23	1		T38	4		T77	2
all_values[0]	auto[1]	auto[1]	auto[1]	114	1			T38	1		T76	1		T118	2
all_values[1]	auto[0]	auto[0]	auto[0]	219	1			T23	3		T38	7		T77	1
all_values[1]	auto[0]	auto[1]	auto[0]	188	1			T23	1		T38	1		T76	4
all_values[1]	auto[1]	auto[0]	auto[1]	151	1			T38	3		T77	2		T78	4
all_values[1]	auto[1]	auto[1]	auto[1]	138	1			T78	1		T119	1		T120	1
all_values[2]	auto[0]	auto[0]	auto[0]	145	1			T23	1		T38	1		T77	2
all_values[2]	auto[0]	auto[0]	auto[1]	59	1			T118	1		T120	1		T121	1
all_values[2]	auto[0]	auto[1]	auto[0]	134	1			T38	2		T76	3		T77	1
all_values[2]	auto[0]	auto[1]	auto[1]	65	1			T23	1		T38	1		T119	2
all_values[2]	auto[1]	auto[0]	auto[1]	152	1			T23	2		T38	2		T77	1
all_values[2]	auto[1]	auto[1]	auto[1]	141	1			T38	5		T76	1		T78	2
all_values[3]	auto[0]	auto[0]	auto[0]	144	1			T38	2		T77	1		T78	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1			T23	2		T38	2		T77	1
all_values[3]	auto[0]	auto[1]	auto[0]	124	1			T38	1		T76	1		T78	2
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T76	1		T77	1		T78	1
all_values[3]	auto[1]	auto[0]	auto[1]	168	1			T23	2		T38	4		T76	1
all_values[3]	auto[1]	auto[1]	auto[1]	127	1			T38	2		T76	1		T78	2
all_values[4]	auto[0]	auto[0]	auto[0]	133	1			T23	1		T38	1		T76	2
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T38	1		T77	2		T118	2
all_values[4]	auto[0]	auto[1]	auto[0]	110	1			T23	1		T38	1		T76	2
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T23	1		T38	3		T120	1
all_values[4]	auto[1]	auto[0]	auto[1]	173	1			T38	2		T78	2		T119	1
all_values[4]	auto[1]	auto[1]	auto[1]	124	1			T23	1		T38	3		T77	1
all_values[5]	auto[0]	auto[0]	auto[0]	128	1			T23	1		T38	1		T76	1
all_values[5]	auto[0]	auto[0]	auto[1]	72	1			T121	1		T122	2		T123	2
all_values[5]	auto[0]	auto[1]	auto[0]	122	1			T23	1		T38	3		T76	1
all_values[5]	auto[0]	auto[1]	auto[1]	78	1			T38	2		T77	1		T78	1
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T23	1		T38	3		T76	2
all_values[5]	auto[1]	auto[1]	auto[1]	122	1			T23	1		T38	2		T77	1
all_values[6]	auto[0]	auto[0]	auto[0]	134	1			T23	2		T38	1		T76	1
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T23	1		T38	1		T78	1
all_values[6]	auto[0]	auto[1]	auto[0]	116	1			T38	1		T77	3		T78	2
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T38	1		T76	2		T78	1
all_values[6]	auto[1]	auto[0]	auto[1]	150	1			T38	5		T76	1		T78	1
all_values[6]	auto[1]	auto[1]	auto[1]	145	1			T23	1		T38	2		T78	2
all_values[7]	auto[0]	auto[0]	auto[0]	131	1			T23	3		T38	3		T76	1
all_values[7]	auto[0]	auto[0]	auto[1]	80	1			T38	1		T78	2		T120	1
all_values[7]	auto[0]	auto[1]	auto[0]	117	1			T23	1		T38	4		T76	3
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T78	1		T118	1		T119	2
all_values[7]	auto[1]	auto[0]	auto[1]	166	1			T38	3		T77	1		T118	1
all_values[7]	auto[1]	auto[1]	auto[1]	126	1			T77	1		T78	2		T118	1
all_values[8]	auto[0]	auto[0]	auto[1]	205	1			T23	1		T38	5		T77	1
all_values[8]	auto[0]	auto[1]	auto[1]	194	1			T23	1		T38	4		T76	1
all_values[8]	auto[1]	auto[0]	auto[1]	151	1			T23	1		T38	2		T76	2
all_values[8]	auto[1]	auto[1]	auto[1]	146	1			T23	1		T76	1		T78	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal