Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	982047	0	0
ctrl_rd_A	2147483647	19257	0	0
intr_enable_rd_A	2147483647	18034	0	0
ovrd_rd_A	2147483647	18963	0	0
timeout_ctrl_rd_A	2147483647	19074	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	982047	0	0
T12	284143	10359	0	0
T19	108074	2798	0	0
T21	0	15590	0	0
T22	369045	0	0	0
T25	103007	0	0	0
T28	383126	0	0	0
T29	175940	0	0	0
T30	5493	0	0	0
T31	1136	0	0	0
T34	0	3106	0	0
T35	0	9095	0	0
T36	0	7442	0	0
T37	0	12308	0	0
T38	0	7950	0	0
T39	0	15075	0	0
T40	0	1066	0	0
T41	181486	0	0	0
T42	18753	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19257	0	0
T19	108074	259	0	0
T20	340011	0	0	0
T22	369045	0	0	0
T23	54483	0	0	0
T28	383126	0	0	0
T35	0	1109	0	0
T38	0	973	0	0
T42	18753	0	0	0
T43	619168	0	0	0
T80	0	773	0	0
T81	0	331	0	0
T82	0	644	0	0
T83	0	953	0	0
T84	0	359	0	0
T85	0	669	0	0
T86	0	1094	0	0
T87	75904	0	0	0
T88	529112	0	0	0
T89	529968	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18034	0	0
T19	108074	274	0	0
T20	340011	0	0	0
T22	369045	0	0	0
T23	54483	0	0	0
T28	383126	0	0	0
T35	0	1141	0	0
T38	0	777	0	0
T42	18753	0	0	0
T43	619168	0	0	0
T80	0	665	0	0
T81	0	413	0	0
T82	0	484	0	0
T83	0	990	0	0
T84	0	361	0	0
T85	0	603	0	0
T87	75904	0	0	0
T88	529112	0	0	0
T89	529968	0	0	0
T90	0	13	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18963	0	0
T19	108074	297	0	0
T20	340011	0	0	0
T22	369045	0	0	0
T23	54483	0	0	0
T28	383126	0	0	0
T35	0	1157	0	0
T38	0	825	0	0
T42	18753	0	0	0
T43	619168	0	0	0
T80	0	767	0	0
T81	0	465	0	0
T82	0	644	0	0
T83	0	1069	0	0
T84	0	386	0	0
T85	0	734	0	0
T86	0	1362	0	0
T87	75904	0	0	0
T88	529112	0	0	0
T89	529968	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19074	0	0
T19	108074	190	0	0
T20	340011	0	0	0
T22	369045	0	0	0
T23	54483	0	0	0
T28	383126	0	0	0
T35	0	1132	0	0
T38	0	875	0	0
T42	18753	0	0	0
T43	619168	0	0	0
T80	0	879	0	0
T81	0	374	0	0
T82	0	568	0	0
T83	0	1055	0	0
T84	0	346	0	0
T85	0	669	0	0
T86	0	1308	0	0
T87	75904	0	0	0
T88	529112	0	0	0
T89	529968	0	0	0