Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	126234	1			T3	2		T4	2		T5	2
all_values[1]	126234	1			T3	2		T4	2		T5	2
all_values[2]	126234	1			T3	2		T4	2		T5	2
all_values[3]	126234	1			T3	2		T4	2		T5	2
all_values[4]	126234	1			T3	2		T4	2		T5	2
all_values[5]	126234	1			T3	2		T4	2		T5	2
all_values[6]	126234	1			T3	2		T4	2		T5	2
all_values[7]	126234	1			T3	2		T4	2		T5	2
all_values[8]	126234	1			T3	2		T4	2		T5	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

573187

1

T3

18

T4

18

T5

18

auto[1]

562919

1

T6

32

T7

27

T8

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1046303

1

T3

13

T4

13

T5

13

auto[1]

89803

1

T3

5

T4

5

T5

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	37743	1			T12	6		T16	1		T28	9
all_values[0]	auto[0]	auto[1]	23565	1			T3	2		T4	2		T5	2
all_values[0]	auto[1]	auto[0]	43358	1			T7	1		T11	1		T16	3
all_values[0]	auto[1]	auto[1]	21568	1			T6	3		T7	2		T9	1
all_values[1]	auto[0]	auto[0]	66708	1			T3	2		T4	2		T5	2
all_values[1]	auto[0]	auto[1]	1652	1			T12	4		T18	17		T51	1
all_values[1]	auto[1]	auto[0]	56259	1			T6	1		T7	1		T9	1
all_values[1]	auto[1]	auto[1]	1615	1			T6	7		T12	20		T17	10
all_values[2]	auto[0]	auto[0]	60580	1			T3	1		T4	1		T5	1
all_values[2]	auto[0]	auto[1]	2888	1			T3	1		T4	1		T5	1
all_values[2]	auto[1]	auto[0]	60261	1			T6	6		T7	1		T24	1
all_values[2]	auto[1]	auto[1]	2505	1			T6	1		T7	1		T16	2
all_values[3]	auto[0]	auto[0]	62455	1			T3	2		T4	2		T5	2
all_values[3]	auto[0]	auto[1]	356	1			T12	4		T17	1		T18	2
all_values[3]	auto[1]	auto[0]	63086	1			T6	1		T7	1		T8	1
all_values[3]	auto[1]	auto[1]	337	1			T12	1		T99	1		T148	3
all_values[4]	auto[0]	auto[0]	61777	1			T3	2		T4	2		T5	2
all_values[4]	auto[0]	auto[1]	379	1			T12	4		T18	16		T283	4
all_values[4]	auto[1]	auto[0]	63604	1			T6	9		T7	4		T8	1
all_values[4]	auto[1]	auto[1]	474	1			T12	12		T20	4		T99	3
all_values[5]	auto[0]	auto[0]	60453	1			T3	2		T4	2		T5	2
all_values[5]	auto[0]	auto[1]	191	1			T99	3		T25	1		T103	1
all_values[5]	auto[1]	auto[0]	65378	1			T6	3		T7	5		T8	1
all_values[5]	auto[1]	auto[1]	212	1			T99	1		T25	1		T100	2
all_values[6]	auto[0]	auto[0]	66975	1			T3	2		T4	2		T5	2
all_values[6]	auto[0]	auto[1]	198	1			T25	1		T100	4		T103	3
all_values[6]	auto[1]	auto[0]	58864	1			T6	1		T7	4		T10	1
all_values[6]	auto[1]	auto[1]	197	1			T99	2		T25	1		T27	2
all_values[7]	auto[0]	auto[0]	63604	1			T3	2		T4	2		T5	2
all_values[7]	auto[0]	auto[1]	422	1			T12	11		T18	5		T284	2
all_values[7]	auto[1]	auto[0]	61862	1			T7	2		T9	1		T12	29
all_values[7]	auto[1]	auto[1]	346	1			T17	1		T18	1		T20	2
all_values[8]	auto[0]	auto[0]	46783	1			T11	1		T12	5		T16	4
all_values[8]	auto[0]	auto[1]	16458	1			T3	2		T4	2		T5	2
all_values[8]	auto[1]	auto[0]	46553	1			T7	1		T12	17		T108	4
all_values[8]	auto[1]	auto[1]	16440	1			T7	4		T9	1		T24	1