Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	79300	1			T1	2		T2	1		T4	2
all_values[1]	79300	1			T1	2		T2	1		T4	2
all_values[2]	79300	1			T1	2		T2	1		T4	2
all_values[3]	79300	1			T1	2		T2	1		T4	2
all_values[4]	79300	1			T1	2		T2	1		T4	2
all_values[5]	79300	1			T1	2		T2	1		T4	2
all_values[6]	79300	1			T1	2		T2	1		T4	2
all_values[7]	79300	1			T1	2		T2	1		T4	2
all_values[8]	79300	1			T1	2		T2	1		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

374699

1

T1

18

T2

5

T4

18

auto[1]

339001

1

T2

4

T7

68

T8

41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645968

1

T1

13

T2

7

T4

13

auto[1]

67732

1

T1

5

T2

2

T4

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	26740	1			T12	130		T41	3		T29	40
all_values[0]	auto[0]	auto[1]	17273	1			T1	2		T4	2		T6	2
all_values[0]	auto[1]	auto[0]	19580	1			T7	10		T8	5		T11	14
all_values[0]	auto[1]	auto[1]	15707	1			T2	1		T8	2		T11	2
all_values[1]	auto[0]	auto[0]	41570	1			T1	2		T4	2		T6	2
all_values[1]	auto[0]	auto[1]	1390	1			T11	7		T19	6		T46	7
all_values[1]	auto[1]	auto[0]	34998	1			T2	1		T7	8		T8	2
all_values[1]	auto[1]	auto[1]	1342	1			T11	4		T19	7		T16	4
all_values[2]	auto[0]	auto[0]	42172	1			T1	1		T4	1		T6	1
all_values[2]	auto[0]	auto[1]	2306	1			T1	1		T4	1		T6	1
all_values[2]	auto[1]	auto[0]	32845	1			T2	1		T7	6		T8	2
all_values[2]	auto[1]	auto[1]	1977	1			T7	4		T11	1		T29	2
all_values[3]	auto[0]	auto[0]	43152	1			T1	2		T4	2		T6	2
all_values[3]	auto[0]	auto[1]	268	1			T19	4		T21	3		T18	1
all_values[3]	auto[1]	auto[0]	35607	1			T2	1		T7	12		T8	6
all_values[3]	auto[1]	auto[1]	273	1			T19	3		T16	2		T17	5
all_values[4]	auto[0]	auto[0]	38749	1			T1	2		T2	1		T4	2
all_values[4]	auto[0]	auto[1]	319	1			T19	7		T16	4		T21	2
all_values[4]	auto[1]	auto[0]	39843	1			T7	2		T8	3		T9	1
all_values[4]	auto[1]	auto[1]	389	1			T19	7		T24	6		T258	10
all_values[5]	auto[0]	auto[0]	40667	1			T1	2		T2	1		T4	2
all_values[5]	auto[0]	auto[1]	165	1			T19	6		T21	1		T34	1
all_values[5]	auto[1]	auto[0]	38319	1			T7	12		T8	3		T9	1
all_values[5]	auto[1]	auto[1]	149	1			T19	4		T21	2		T39	2
all_values[6]	auto[0]	auto[0]	43070	1			T1	2		T2	1		T4	2
all_values[6]	auto[0]	auto[1]	167	1			T19	2		T21	1		T39	6
all_values[6]	auto[1]	auto[0]	35923	1			T7	2		T8	3		T11	14
all_values[6]	auto[1]	auto[1]	140	1			T19	8		T21	1		T39	2
all_values[7]	auto[0]	auto[0]	39826	1			T1	2		T2	1		T4	2
all_values[7]	auto[0]	auto[1]	309	1			T19	2		T108	2		T107	3
all_values[7]	auto[1]	auto[0]	38850	1			T7	2		T8	7		T9	1
all_values[7]	auto[1]	auto[1]	315	1			T19	12		T16	2		T34	2
all_values[8]	auto[0]	auto[0]	24312	1			T7	2		T8	1		T11	14
all_values[8]	auto[0]	auto[1]	12244	1			T1	2		T2	1		T4	2
all_values[8]	auto[1]	auto[0]	29745	1			T7	8		T8	7		T12	69
all_values[8]	auto[1]	auto[1]	12999	1			T7	2		T8	1		T9	1