Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total tests in report: 1315
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
76.61 76.61 94.37 94.37 79.53 79.53 94.19 94.19 90.97 90.97 94.66 94.66 5.94 5.94 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2574184931
82.10 5.49 97.49 3.12 87.65 8.12 96.34 2.15 93.29 2.31 96.14 1.48 21.72 15.78 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.448868201
84.90 2.80 98.49 1.01 90.82 3.18 96.84 0.51 95.60 2.31 96.14 0.00 31.50 9.78 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_stress_all.3783925735
86.73 1.83 98.49 0.00 91.53 0.71 96.84 0.00 95.83 0.23 96.14 0.00 41.54 10.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_stress_all.2058547391
88.34 1.61 98.49 0.00 91.53 0.00 96.84 0.00 95.83 0.00 97.33 1.19 49.99 8.44 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.465201681
89.77 1.44 98.99 0.50 94.00 2.47 96.97 0.13 97.45 1.62 97.33 0.00 53.89 3.91 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.254657265
91.00 1.22 98.99 0.00 94.00 0.00 96.97 0.00 97.45 0.00 97.33 0.00 61.23 7.34 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_stress_all.3562694716
91.85 0.85 98.99 0.00 94.00 0.00 96.97 0.00 97.45 0.00 97.33 0.00 66.36 5.13 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_stress_all.3682204357
92.62 0.77 98.99 0.00 95.76 1.76 96.97 0.00 97.45 0.00 97.33 0.00 69.20 2.84 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_intr.3223430604
93.32 0.70 98.99 0.00 95.76 0.00 96.97 0.00 97.45 0.00 97.33 0.00 73.40 4.20 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.2153107038
93.99 0.67 98.99 0.00 95.76 0.00 96.97 0.00 97.45 0.00 97.33 0.00 77.40 4.00 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_intr.2030733717
94.55 0.56 99.10 0.10 96.12 0.35 99.24 2.27 97.69 0.23 97.63 0.30 77.51 0.11 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_sec_cm.2307386007
95.08 0.53 99.10 0.00 96.12 0.00 99.24 0.00 97.69 0.00 97.63 0.00 80.70 3.18 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_stress_all.3584844235
95.57 0.50 99.10 0.00 96.12 0.00 99.24 0.00 97.69 0.00 97.63 0.00 83.68 2.98 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.276736063
95.95 0.38 99.10 0.00 96.12 0.00 99.24 0.00 97.69 0.00 97.63 0.00 85.93 2.26 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.2371090422
96.22 0.27 99.10 0.00 96.12 0.00 99.24 0.00 97.69 0.00 97.63 0.00 87.54 1.60 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.3345002499
96.48 0.26 99.10 0.00 96.12 0.00 99.24 0.00 97.69 0.00 99.11 1.48 87.60 0.07 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.4016658739
96.72 0.24 99.10 0.00 96.12 0.00 99.24 0.00 97.69 0.00 99.11 0.00 89.07 1.47 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_stress_all.2704123974
96.95 0.23 99.10 0.00 96.24 0.12 99.75 0.51 97.92 0.23 99.11 0.00 89.61 0.54 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_intr.3599545668
97.15 0.19 99.10 0.00 96.24 0.00 99.75 0.00 97.92 0.00 99.11 0.00 90.77 1.15 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_fifo_full.4140090697
97.31 0.16 99.10 0.00 97.06 0.82 99.75 0.00 97.92 0.00 99.11 0.00 90.92 0.16 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3029046450
97.46 0.15 99.10 0.00 97.06 0.00 99.75 0.00 97.92 0.00 99.41 0.30 91.51 0.59 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.913404522
97.60 0.14 99.10 0.00 97.29 0.24 99.75 0.00 98.38 0.46 99.41 0.00 91.67 0.16 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_loopback.2232801781
97.73 0.13 99.10 0.00 97.29 0.00 99.75 0.00 98.38 0.00 99.41 0.00 92.44 0.77 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.2726832102
97.85 0.12 99.10 0.00 97.29 0.00 99.75 0.00 98.38 0.00 99.41 0.00 93.18 0.75 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_fifo_reset.4265903909
97.96 0.11 99.10 0.00 97.29 0.00 99.75 0.00 98.38 0.00 99.41 0.00 93.84 0.65 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_noise_filter.3053545251
98.07 0.11 99.10 0.00 97.29 0.00 99.75 0.00 98.38 0.00 99.41 0.00 94.47 0.63 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_stress_all.4273463060
98.17 0.10 99.10 0.00 97.65 0.35 100.00 0.25 98.38 0.00 99.41 0.00 94.47 0.00 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_alert_test.2284860007
98.27 0.10 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.59 94.47 0.00 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.3682740130
98.34 0.08 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 94.92 0.45 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_fifo_full.776460711
98.41 0.07 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.33 0.41 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.3011883664
98.47 0.06 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 95.69 0.36 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_stress_all.728836701
98.52 0.05 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.00 0.32 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.1871714962
98.57 0.05 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.27 0.27 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_noise_filter.537352905
98.61 0.04 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.52 0.25 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.540934638
98.64 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.73 0.20 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_fifo_full.723615982
98.67 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 96.91 0.18 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_noise_filter.2166444328
98.70 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.06 0.16 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2647581758
98.72 0.03 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.22 0.16 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_tx_rx.2218535269
98.75 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.36 0.14 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_tx_rx.2024540246
98.77 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.49 0.14 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.2846993520
98.79 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.63 0.14 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/96.uart_fifo_reset.82145565
98.81 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.74 0.11 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.1921072573
98.83 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.86 0.11 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/24.uart_fifo_reset.4114183268
98.85 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 97.97 0.11 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/27.uart_fifo_reset.551600702
98.87 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.08 0.11 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/46.uart_fifo_reset.3465510017
98.88 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.17 0.09 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.2312868866
98.90 0.02 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.26 0.09 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_noise_filter.1393552820
98.91 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.33 0.07 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/164.uart_fifo_reset.3558832618
98.92 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.40 0.07 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/166.uart_fifo_reset.3476646592
98.93 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.46 0.07 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.3611738823
98.94 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.53 0.07 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/57.uart_fifo_reset.2362932332
98.95 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.60 0.07 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/65.uart_fifo_reset.3476929287
98.96 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.65 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.2974403774
98.97 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.69 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_tx_rx.1977096511
98.98 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.74 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_fifo_reset.798012332
98.98 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.78 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2771655849
98.99 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.83 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_fifo_reset.1471184525
99.00 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.87 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/148.uart_fifo_reset.359779513
99.01 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.92 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.2936592675
99.01 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/162.uart_fifo_reset.593545758
99.02 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/285.uart_fifo_reset.1827174361
99.03 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.05 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1907258992
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.10 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.2133333969
99.04 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.14 0.05 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/73.uart_fifo_reset.448382939
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.16 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_loopback.957613390
99.05 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.19 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_fifo_reset.942055303
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.21 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/100.uart_fifo_reset.4153218526
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.23 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/111.uart_fifo_reset.4210932681
99.06 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.25 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/115.uart_fifo_reset.1299278367
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.28 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/118.uart_fifo_reset.3344670421
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.30 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_fifo_full.1571093734
99.07 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.32 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/14.uart_intr.2731794425
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.35 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/141.uart_fifo_reset.3715709987
99.08 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.37 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/143.uart_fifo_reset.354529783
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.39 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/15.uart_noise_filter.1925476754
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.41 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1688704177
99.09 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.44 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/186.uart_fifo_reset.955116584
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.46 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1830342725
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.48 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/231.uart_fifo_reset.1498752483
99.10 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.50 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/234.uart_fifo_reset.116790189
99.11 0.01 99.10 0.00 97.65 0.00 100.00 0.00 98.38 0.00 100.00 0.00 99.53 0.02 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/33.uart_fifo_reset.2394804882

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.651995232
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.434696277
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1392127817
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2778293449
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1358196796
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3809620522
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2088037488
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3686660520
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.806699457
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.4045979972
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3698094083
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2768348818
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.1191106604
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3569326131
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.2502096782
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.1888694860
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4003176442
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.3291326040
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.356446922
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2795671033
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.2351209030
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.3686218218
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/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2554335831
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/81.uart_fifo_reset.1280447184
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.3476444469
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/82.uart_fifo_reset.211524112
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.3937091542
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1311470905
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.1655247912
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/84.uart_fifo_reset.1276913436
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.2969979724
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/85.uart_fifo_reset.84657225
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.889591593
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3428114391
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.3969267670
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/87.uart_fifo_reset.42478842
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.3239164708
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/88.uart_fifo_reset.933326500
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3887966879
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2633445123
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.193686724
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_alert_test.3067119458
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_fifo_full.1541212013
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.364469988
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_intr.2089699553
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.3381489014
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_loopback.426188956
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_noise_filter.4174494105
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_perf.4208628930
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_rx_oversample.4294194864
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3517156075
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.4025965032
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_smoke.3362881554
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_stress_all.1421996156
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3064535620
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1256374639
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_tx_rx.3079015509
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/90.uart_fifo_reset.20397237
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.4168564732
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/91.uart_fifo_reset.2710684747
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.2890624049
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3162261412
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.1695317190
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2015952233
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2725770449
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.4144478019
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/95.uart_fifo_reset.427833764
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.3252714274
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.2557878561
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/97.uart_fifo_reset.2551010837
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2269185647
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2044922072
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.3643642100
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/99.uart_fifo_reset.972922376
/workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.3149223789



Total test records in report: 1315
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_alert_test.2284860007 Feb 09 06:35:22 AM UTC 25 Feb 09 06:35:24 AM UTC 25 47285630 ps
T2 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_sec_cm.2307386007 Feb 09 06:35:22 AM UTC 25 Feb 09 06:35:24 AM UTC 25 103025178 ps
T3 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.3479344851 Feb 09 06:35:19 AM UTC 25 Feb 09 06:35:26 AM UTC 25 2252286388 ps
T4 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_smoke.1197969159 Feb 09 06:35:25 AM UTC 25 Feb 09 06:35:28 AM UTC 25 273544589 ps
T5 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_smoke.1386812412 Feb 09 06:35:18 AM UTC 25 Feb 09 06:35:33 AM UTC 25 5283057286 ps
T6 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2574184931 Feb 09 06:35:18 AM UTC 25 Feb 09 06:35:50 AM UTC 25 47742228771 ps
T7 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.1638254869 Feb 09 06:35:20 AM UTC 25 Feb 09 06:35:50 AM UTC 25 6969470380 ps
T8 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_rx_oversample.94521898 Feb 09 06:35:35 AM UTC 25 Feb 09 06:35:50 AM UTC 25 1797102770 ps
T9 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_rx_oversample.3851847711 Feb 09 06:35:19 AM UTC 25 Feb 09 06:35:54 AM UTC 25 3902052067 ps
T10 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_loopback.957613390 Feb 09 06:35:21 AM UTC 25 Feb 09 06:35:57 AM UTC 25 5634697187 ps
T13 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.1079284405 Feb 09 06:35:20 AM UTC 25 Feb 09 06:35:58 AM UTC 25 6918684699 ps
T14 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.1008913359 Feb 09 06:35:52 AM UTC 25 Feb 09 06:36:03 AM UTC 25 4396369310 ps
T15 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.1357627256 Feb 09 06:35:58 AM UTC 25 Feb 09 06:36:03 AM UTC 25 3772024232 ps
T24 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_loopback.845755969 Feb 09 06:35:59 AM UTC 25 Feb 09 06:36:04 AM UTC 25 1438513714 ps
T11 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.254657265 Feb 09 06:35:29 AM UTC 25 Feb 09 06:36:04 AM UTC 25 15217282845 ps
T12 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_intr.3223430604 Feb 09 06:35:19 AM UTC 25 Feb 09 06:36:05 AM UTC 25 46541058205 ps
T30 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_sec_cm.8002825 Feb 09 06:36:05 AM UTC 25 Feb 09 06:36:08 AM UTC 25 120236246 ps
T32 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_alert_test.3622952866 Feb 09 06:36:08 AM UTC 25 Feb 09 06:36:10 AM UTC 25 19211746 ps
T98 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_smoke.363149388 Feb 09 06:36:08 AM UTC 25 Feb 09 06:36:12 AM UTC 25 741058659 ps
T16 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2647581758 Feb 09 06:35:30 AM UTC 25 Feb 09 06:36:14 AM UTC 25 36230990174 ps
T28 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_fifo_full.3781720464 Feb 09 06:35:18 AM UTC 25 Feb 09 06:36:24 AM UTC 25 81151712206 ps
T102 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.3456142429 Feb 09 06:35:55 AM UTC 25 Feb 09 06:36:35 AM UTC 25 35213274682 ps
T19 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_rx_oversample.222802637 Feb 09 06:36:19 AM UTC 25 Feb 09 06:36:39 AM UTC 25 5221442292 ps
T107 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.846469746 Feb 09 06:36:35 AM UTC 25 Feb 09 06:36:41 AM UTC 25 2692321134 ps
T17 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_intr.2769598341 Feb 09 06:36:25 AM UTC 25 Feb 09 06:36:50 AM UTC 25 31087902228 ps
T21 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.116547386 Feb 09 06:36:41 AM UTC 25 Feb 09 06:36:51 AM UTC 25 1199085104 ps
T108 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_fifo_full.2255136470 Feb 09 06:36:13 AM UTC 25 Feb 09 06:36:54 AM UTC 25 11265118455 ps
T142 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_tx_rx.2071446906 Feb 09 06:35:18 AM UTC 25 Feb 09 06:36:55 AM UTC 25 32940022078 ps
T31 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_sec_cm.5072634 Feb 09 06:36:56 AM UTC 25 Feb 09 06:36:59 AM UTC 25 246912905 ps
T33 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_alert_test.726888324 Feb 09 06:36:59 AM UTC 25 Feb 09 06:37:02 AM UTC 25 13823035 ps
T18 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_intr.3599545668 Feb 09 06:35:51 AM UTC 25 Feb 09 06:37:04 AM UTC 25 51087335738 ps
T289 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_tx_rx.2163455650 Feb 09 06:36:12 AM UTC 25 Feb 09 06:37:05 AM UTC 25 31076726867 ps
T29 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_tx_rx.2024540246 Feb 09 06:35:25 AM UTC 25 Feb 09 06:37:05 AM UTC 25 136257773179 ps
T321 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_smoke.1183810433 Feb 09 06:37:02 AM UTC 25 Feb 09 06:37:10 AM UTC 25 926200473 ps
T143 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.3068859718 Feb 09 06:36:15 AM UTC 25 Feb 09 06:37:13 AM UTC 25 129968031711 ps
T428 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_rx_oversample.2341153053 Feb 09 06:37:09 AM UTC 25 Feb 09 06:37:14 AM UTC 25 2783633783 ps
T22 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_loopback.3088202143 Feb 09 06:36:42 AM UTC 25 Feb 09 06:37:15 AM UTC 25 11166382944 ps
T50 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.634899060 Feb 09 06:35:21 AM UTC 25 Feb 09 06:37:22 AM UTC 25 64018842852 ps
T325 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.1825052700 Feb 09 06:37:15 AM UTC 25 Feb 09 06:37:24 AM UTC 25 5070772169 ps
T51 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_noise_filter.1355335622 Feb 09 06:35:19 AM UTC 25 Feb 09 06:37:33 AM UTC 25 461326823460 ps
T23 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_loopback.3782363343 Feb 09 06:37:25 AM UTC 25 Feb 09 06:37:34 AM UTC 25 5773842005 ps
T133 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.2908403900 Feb 09 06:37:16 AM UTC 25 Feb 09 06:37:35 AM UTC 25 47999361240 ps
T52 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_noise_filter.2811989805 Feb 09 06:35:51 AM UTC 25 Feb 09 06:37:36 AM UTC 25 277400932548 ps
T20 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_intr.1918421031 Feb 09 06:37:11 AM UTC 25 Feb 09 06:37:48 AM UTC 25 20761789684 ps
T144 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_tx_rx.3145048580 Feb 09 06:37:05 AM UTC 25 Feb 09 06:37:50 AM UTC 25 52734040406 ps
T53 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.913404522 Feb 09 06:35:18 AM UTC 25 Feb 09 06:37:51 AM UTC 25 90829882980 ps
T112 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_sec_cm.3823721807 Feb 09 06:37:49 AM UTC 25 Feb 09 06:37:52 AM UTC 25 231914408 ps
T429 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_alert_test.2371329062 Feb 09 06:37:50 AM UTC 25 Feb 09 06:37:52 AM UTC 25 22407938 ps
T347 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_smoke.3349140208 Feb 09 06:37:51 AM UTC 25 Feb 09 06:37:55 AM UTC 25 695778455 ps
T301 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.3352324033 Feb 09 06:37:23 AM UTC 25 Feb 09 06:38:09 AM UTC 25 7102776905 ps
T131 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_fifo_full.776460711 Feb 09 06:35:27 AM UTC 25 Feb 09 06:38:14 AM UTC 25 173324987743 ps
T402 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_rx_oversample.1833031401 Feb 09 06:38:05 AM UTC 25 Feb 09 06:38:21 AM UTC 25 4239736507 ps
T284 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.3711598537 Feb 09 06:36:39 AM UTC 25 Feb 09 06:38:22 AM UTC 25 90561655563 ps
T145 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_tx_rx.2574701484 Feb 09 06:37:52 AM UTC 25 Feb 09 06:38:24 AM UTC 25 8567272612 ps
T356 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.4187923917 Feb 09 06:38:25 AM UTC 25 Feb 09 06:38:32 AM UTC 25 869853749 ps
T99 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/0.uart_stress_all.3783925735 Feb 09 06:35:21 AM UTC 25 Feb 09 06:38:37 AM UTC 25 344648297362 ps
T113 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_sec_cm.2994436439 Feb 09 06:38:39 AM UTC 25 Feb 09 06:38:41 AM UTC 25 131274065 ps
T430 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_alert_test.4230351731 Feb 09 06:38:42 AM UTC 25 Feb 09 06:38:44 AM UTC 25 45703190 ps
T132 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_fifo_full.3682631918 Feb 09 06:37:54 AM UTC 25 Feb 09 06:38:45 AM UTC 25 56454325190 ps
T431 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_loopback.2341823654 Feb 09 06:38:25 AM UTC 25 Feb 09 06:38:46 AM UTC 25 5084368842 ps
T146 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_fifo_reset.1001517092 Feb 09 06:37:58 AM UTC 25 Feb 09 06:38:49 AM UTC 25 206875569958 ps
T137 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_intr.1698378105 Feb 09 06:38:10 AM UTC 25 Feb 09 06:38:56 AM UTC 25 46297062548 ps
T329 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_smoke.1380955686 Feb 09 06:38:45 AM UTC 25 Feb 09 06:39:02 AM UTC 25 5667930510 ps
T54 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.497903275 Feb 09 06:38:23 AM UTC 25 Feb 09 06:39:07 AM UTC 25 28518489238 ps
T157 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.3969892667 Feb 09 06:37:56 AM UTC 25 Feb 09 06:39:11 AM UTC 25 183096509530 ps
T401 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_rx_oversample.2506234514 Feb 09 06:38:56 AM UTC 25 Feb 09 06:39:16 AM UTC 25 3239961873 ps
T55 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_noise_filter.2000247336 Feb 09 06:38:15 AM UTC 25 Feb 09 06:39:16 AM UTC 25 19177727401 ps
T349 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.3841375452 Feb 09 06:39:12 AM UTC 25 Feb 09 06:39:16 AM UTC 25 3140598991 ps
T56 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.3039824680 Feb 09 06:39:17 AM UTC 25 Feb 09 06:39:24 AM UTC 25 675140340 ps
T151 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_fifo_full.723615982 Feb 09 06:38:47 AM UTC 25 Feb 09 06:39:38 AM UTC 25 32302165710 ps
T174 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.2726832102 Feb 09 06:38:50 AM UTC 25 Feb 09 06:39:43 AM UTC 25 105146239023 ps
T432 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_loopback.2965389342 Feb 09 06:39:17 AM UTC 25 Feb 09 06:39:45 AM UTC 25 5716300468 ps
T433 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_alert_test.1969394130 Feb 09 06:39:45 AM UTC 25 Feb 09 06:39:47 AM UTC 25 41390296 ps
T57 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_fifo_reset.858014661 Feb 09 06:37:06 AM UTC 25 Feb 09 06:39:49 AM UTC 25 75553609577 ps
T292 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.4279768275 Feb 09 06:37:35 AM UTC 25 Feb 09 06:39:53 AM UTC 25 98894941521 ps
T330 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_smoke.3926564215 Feb 09 06:39:48 AM UTC 25 Feb 09 06:39:59 AM UTC 25 5869171335 ps
T101 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_intr.2263793472 Feb 09 06:39:03 AM UTC 25 Feb 09 06:40:05 AM UTC 25 54895135899 ps
T342 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_stress_all.1400755887 Feb 09 06:38:38 AM UTC 25 Feb 09 06:40:24 AM UTC 25 12541333816 ps
T306 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_noise_filter.3053545251 Feb 09 06:36:25 AM UTC 25 Feb 09 06:40:26 AM UTC 25 86976638706 ps
T344 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.3831367567 Feb 09 06:38:21 AM UTC 25 Feb 09 06:40:30 AM UTC 25 75787591424 ps
T318 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.1021175829 Feb 09 06:38:33 AM UTC 25 Feb 09 06:40:31 AM UTC 25 47240959532 ps
T303 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.1239538715 Feb 09 06:40:27 AM UTC 25 Feb 09 06:40:33 AM UTC 25 2317678988 ps
T283 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_intr.1064017107 Feb 09 06:40:21 AM UTC 25 Feb 09 06:40:33 AM UTC 25 6850603358 ps
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T404 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_loopback.2232801781 Feb 09 06:40:34 AM UTC 25 Feb 09 06:40:47 AM UTC 25 5180829721 ps
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T305 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_perf.216196843 Feb 09 06:37:34 AM UTC 25 Feb 09 06:40:50 AM UTC 25 7560437877 ps
T315 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_noise_filter.3420863481 Feb 09 06:39:08 AM UTC 25 Feb 09 06:40:51 AM UTC 25 126991409424 ps
T293 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_noise_filter.2881140457 Feb 09 06:37:14 AM UTC 25 Feb 09 06:40:55 AM UTC 25 102203747817 ps
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T362 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_smoke.4228760672 Feb 09 06:40:47 AM UTC 25 Feb 09 06:41:04 AM UTC 25 5808013727 ps
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T371 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.184089787 Feb 09 06:41:05 AM UTC 25 Feb 09 06:41:09 AM UTC 25 4917211972 ps
T359 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.3029890762 Feb 09 06:41:09 AM UTC 25 Feb 09 06:41:12 AM UTC 25 1730082778 ps
T148 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/1.uart_stress_all.2058547391 Feb 09 06:36:05 AM UTC 25 Feb 09 06:41:15 AM UTC 25 438519124578 ps
T299 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_intr.871958163 Feb 09 06:41:02 AM UTC 25 Feb 09 06:41:16 AM UTC 25 15196496294 ps
T184 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.1572578753 Feb 09 06:37:06 AM UTC 25 Feb 09 06:41:25 AM UTC 25 137850856302 ps
T405 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_loopback.1773546027 Feb 09 06:41:13 AM UTC 25 Feb 09 06:41:29 AM UTC 25 11473056607 ps
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T436 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_alert_test.4021766311 Feb 09 06:41:30 AM UTC 25 Feb 09 06:41:32 AM UTC 25 20584114 ps
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T364 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_smoke.3949998001 Feb 09 06:41:33 AM UTC 25 Feb 09 06:41:37 AM UTC 25 649394000 ps
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T149 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_stress_all.1228375474 Feb 09 06:40:39 AM UTC 25 Feb 09 06:41:47 AM UTC 25 109793320080 ps
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T316 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_tx_rx.810013416 Feb 09 06:41:38 AM UTC 25 Feb 09 06:42:12 AM UTC 25 90181888171 ps
T380 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.2905943513 Feb 09 06:42:13 AM UTC 25 Feb 09 06:42:17 AM UTC 25 501270003 ps
T309 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.3509313132 Feb 09 06:41:08 AM UTC 25 Feb 09 06:42:22 AM UTC 25 44446913839 ps
T172 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_fifo_reset.1707739221 Feb 09 06:40:02 AM UTC 25 Feb 09 06:42:22 AM UTC 25 102637517132 ps
T353 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1357494190 Feb 09 06:42:18 AM UTC 25 Feb 09 06:42:22 AM UTC 25 1300615383 ps
T437 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_rx_oversample.1144265588 Feb 09 06:41:48 AM UTC 25 Feb 09 06:42:22 AM UTC 25 5589227629 ps
T438 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_loopback.446986549 Feb 09 06:42:22 AM UTC 25 Feb 09 06:42:26 AM UTC 25 998989833 ps
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T439 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_alert_test.2997409410 Feb 09 06:42:30 AM UTC 25 Feb 09 06:42:32 AM UTC 25 14138226 ps
T295 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_smoke.3362881554 Feb 09 06:42:33 AM UTC 25 Feb 09 06:42:47 AM UTC 25 5385150175 ps
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T300 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_fifo_reset.4172901631 Feb 09 06:38:53 AM UTC 25 Feb 09 06:42:51 AM UTC 25 196106506957 ps
T311 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_tx_rx.3094451544 Feb 09 06:38:46 AM UTC 25 Feb 09 06:43:09 AM UTC 25 52804481787 ps
T296 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_noise_filter.537352905 Feb 09 06:40:25 AM UTC 25 Feb 09 06:43:10 AM UTC 25 152038328787 ps
T25 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.448868201 Feb 09 06:36:54 AM UTC 25 Feb 09 06:43:19 AM UTC 25 93095839699 ps
T41 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_fifo_full.1541212013 Feb 09 06:42:48 AM UTC 25 Feb 09 06:43:24 AM UTC 25 45560191316 ps
T42 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3517156075 Feb 09 06:43:21 AM UTC 25 Feb 09 06:43:31 AM UTC 25 13252055843 ps
T43 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1256374639 Feb 09 06:43:25 AM UTC 25 Feb 09 06:43:45 AM UTC 25 7637443461 ps
T44 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_tx_rx.3079015509 Feb 09 06:42:47 AM UTC 25 Feb 09 06:43:50 AM UTC 25 101983599371 ps
T45 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_intr.2089699553 Feb 09 06:43:02 AM UTC 25 Feb 09 06:43:54 AM UTC 25 123305011071 ps
T46 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_loopback.426188956 Feb 09 06:43:32 AM UTC 25 Feb 09 06:43:59 AM UTC 25 14081307635 ps
T47 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_alert_test.3067119458 Feb 09 06:44:00 AM UTC 25 Feb 09 06:44:02 AM UTC 25 61648639 ps
T48 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_smoke.2127483250 Feb 09 06:44:03 AM UTC 25 Feb 09 06:44:06 AM UTC 25 510825081 ps
T49 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.3011883664 Feb 09 06:36:52 AM UTC 25 Feb 09 06:44:08 AM UTC 25 74053923136 ps
T440 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_rx_oversample.4294194864 Feb 09 06:43:00 AM UTC 25 Feb 09 06:44:11 AM UTC 25 6310321001 ps
T160 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_fifo_reset.4265903909 Feb 09 06:42:53 AM UTC 25 Feb 09 06:44:12 AM UTC 25 40606899670 ps
T302 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.3862805197 Feb 09 06:39:17 AM UTC 25 Feb 09 06:44:12 AM UTC 25 139013800811 ps
T158 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.4037924570 Feb 09 06:42:18 AM UTC 25 Feb 09 06:44:26 AM UTC 25 60867512610 ps
T312 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.4025965032 Feb 09 06:43:11 AM UTC 25 Feb 09 06:44:28 AM UTC 25 79943645150 ps
T297 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_perf.957772470 Feb 09 06:39:17 AM UTC 25 Feb 09 06:44:30 AM UTC 25 14673765207 ps
T285 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/6.uart_tx_rx.2218535269 Feb 09 06:39:49 AM UTC 25 Feb 09 06:44:44 AM UTC 25 84357123942 ps
T307 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_noise_filter.4174494105 Feb 09 06:43:10 AM UTC 25 Feb 09 06:44:48 AM UTC 25 37769190626 ps
T374 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.377799295 Feb 09 06:44:31 AM UTC 25 Feb 09 06:44:50 AM UTC 25 4741842909 ps
T394 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_fifo_full.1571879852 Feb 09 06:44:09 AM UTC 25 Feb 09 06:44:52 AM UTC 25 14179241065 ps
T441 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_rx_oversample.1652106799 Feb 09 06:44:13 AM UTC 25 Feb 09 06:44:58 AM UTC 25 7086319755 ps
T134 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_intr.1919224003 Feb 09 06:44:27 AM UTC 25 Feb 09 06:44:58 AM UTC 25 37053152828 ps
T155 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.2371090422 Feb 09 06:41:41 AM UTC 25 Feb 09 06:44:59 AM UTC 25 143851500954 ps
T442 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_alert_test.3829319913 Feb 09 06:44:59 AM UTC 25 Feb 09 06:45:01 AM UTC 25 78023740 ps
T372 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_smoke.786009845 Feb 09 06:45:00 AM UTC 25 Feb 09 06:45:04 AM UTC 25 554222226 ps
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T375 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.1927956561 Feb 09 06:44:48 AM UTC 25 Feb 09 06:45:16 AM UTC 25 6628727065 ps
T443 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_loopback.362538509 Feb 09 06:44:49 AM UTC 25 Feb 09 06:45:17 AM UTC 25 5489091641 ps
T308 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.3227946642 Feb 09 06:44:46 AM UTC 25 Feb 09 06:45:20 AM UTC 25 15668940710 ps
T322 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_noise_filter.1393552820 Feb 09 06:42:09 AM UTC 25 Feb 09 06:45:21 AM UTC 25 169263283865 ps
T444 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_rx_oversample.598319137 Feb 09 06:45:17 AM UTC 25 Feb 09 06:45:25 AM UTC 25 2434576580 ps
T338 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_tx_rx.3356410360 Feb 09 06:45:02 AM UTC 25 Feb 09 06:45:28 AM UTC 25 12945768532 ps
T393 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.363257004 Feb 09 06:45:22 AM UTC 25 Feb 09 06:45:37 AM UTC 25 35153412690 ps
T334 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.96700306 Feb 09 06:45:29 AM UTC 25 Feb 09 06:45:44 AM UTC 25 6485036594 ps
T156 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.1046157784 Feb 09 06:45:26 AM UTC 25 Feb 09 06:45:50 AM UTC 25 11831271229 ps
T445 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_loopback.1460708268 Feb 09 06:45:29 AM UTC 25 Feb 09 06:46:01 AM UTC 25 8663971382 ps
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T323 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.276736063 Feb 09 06:42:24 AM UTC 25 Feb 09 06:46:05 AM UTC 25 159067991239 ps
T328 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_smoke.2924673910 Feb 09 06:46:05 AM UTC 25 Feb 09 06:46:08 AM UTC 25 313238369 ps
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T310 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_tx_rx.1977096511 Feb 09 06:44:07 AM UTC 25 Feb 09 06:46:20 AM UTC 25 55965298683 ps
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T447 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/4.uart_perf.1350291583 Feb 09 06:38:30 AM UTC 25 Feb 09 06:46:51 AM UTC 25 6173622489 ps
T152 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.2400206704 Feb 09 06:46:14 AM UTC 25 Feb 09 06:46:54 AM UTC 25 20627838957 ps
T195 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_fifo_reset.1281633024 Feb 09 06:46:21 AM UTC 25 Feb 09 06:47:05 AM UTC 25 23851494267 ps
T287 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/11.uart_fifo_full.4140090697 Feb 09 06:45:05 AM UTC 25 Feb 09 06:47:09 AM UTC 25 28651147451 ps
T351 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.130484286 Feb 09 06:47:07 AM UTC 25 Feb 09 06:47:14 AM UTC 25 1830579713 ps
T304 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_noise_filter.3620637629 Feb 09 06:44:29 AM UTC 25 Feb 09 06:47:25 AM UTC 25 116438256048 ps
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T352 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_intr.197399116 Feb 09 06:46:52 AM UTC 25 Feb 09 06:47:37 AM UTC 25 26491226162 ps
T448 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_alert_test.2956252162 Feb 09 06:47:38 AM UTC 25 Feb 09 06:47:40 AM UTC 25 12847031 ps
T319 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.2153107038 Feb 09 06:44:52 AM UTC 25 Feb 09 06:47:41 AM UTC 25 77405213690 ps
T376 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.161688575 Feb 09 06:47:16 AM UTC 25 Feb 09 06:47:41 AM UTC 25 7497060412 ps
T333 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/7.uart_fifo_full.2888488378 Feb 09 06:40:51 AM UTC 25 Feb 09 06:47:45 AM UTC 25 206845167899 ps
T449 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_loopback.485840864 Feb 09 06:47:26 AM UTC 25 Feb 09 06:47:45 AM UTC 25 9232147858 ps
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T294 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.3381489014 Feb 09 06:43:47 AM UTC 25 Feb 09 06:47:48 AM UTC 25 66543913990 ps
T100 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/5.uart_stress_all.3562694716 Feb 09 06:39:43 AM UTC 25 Feb 09 06:47:48 AM UTC 25 358179800129 ps
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T384 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_intr.3742415668 Feb 09 06:47:49 AM UTC 25 Feb 09 06:48:05 AM UTC 25 16563530542 ps
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T451 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.2519725407 Feb 09 06:48:06 AM UTC 25 Feb 09 06:48:10 AM UTC 25 1100768066 ps
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T367 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.4209514915 Feb 09 06:47:50 AM UTC 25 Feb 09 06:48:18 AM UTC 25 157086235029 ps
T452 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_loopback.3470833093 Feb 09 06:48:11 AM UTC 25 Feb 09 06:48:18 AM UTC 25 2759956662 ps
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T313 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.364469988 Feb 09 06:42:52 AM UTC 25 Feb 09 06:48:21 AM UTC 25 92690559826 ps
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T354 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.289528282 Feb 09 06:47:49 AM UTC 25 Feb 09 06:48:26 AM UTC 25 39501473285 ps
T408 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/12.uart_tx_rx.1734263929 Feb 09 06:46:06 AM UTC 25 Feb 09 06:48:28 AM UTC 25 45939436256 ps
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T379 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_fifo_full.3493684950 Feb 09 06:51:13 AM UTC 25 Feb 09 06:51:26 AM UTC 25 28582426540 ps
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T475 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/17.uart_intr.2185283083 Feb 09 06:51:25 AM UTC 25 Feb 09 06:51:42 AM UTC 25 5581942584 ps
T383 /workspaces/repo/scratch/os_regression/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.2936592675 Feb 09 06:50:38 AM UTC 25 Feb 09 06:51:43 AM UTC 25 52832953431 ps
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