Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2669

1

T1

1

T2

21

T3

1

auto[UartRx]

2669

1

T1

1

T2

21

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4705	1			T1	2		T2	42		T3	2
values[1]	48	1			T36	1		T37	1		T40	5
values[2]	59	1			T25	1		T27	2		T34	1
values[3]	57	1			T25	2		T27	3		T40	3
values[4]	47	1			T26	1		T27	2		T34	1
values[5]	55	1			T27	2		T34	1		T35	1
values[6]	67	1			T34	1		T395	1		T115	1
values[7]	66	1			T26	1		T34	1		T36	3
values[8]	67	1			T26	1		T27	1		T36	1
values[9]	74	1			T34	1		T35	2		T36	2
values[10]	65	1			T27	1		T37	1		T39	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2429	1			T1	1		T2	21		T3	1
auto[UartTx]	values[1]	14	1			T40	3		T67	1		T396	1
auto[UartTx]	values[2]	24	1			T34	1		T39	1		T117	2
auto[UartTx]	values[3]	22	1			T25	1		T40	1		T115	1
auto[UartTx]	values[4]	20	1			T26	1		T27	2		T34	1
auto[UartTx]	values[5]	17	1			T27	1		T35	1		T114	2
auto[UartTx]	values[6]	25	1			T395	1		T115	1		T183	1
auto[UartTx]	values[7]	24	1			T36	1		T37	1		T397	1
auto[UartTx]	values[8]	25	1			T26	1		T398	1		T114	1
auto[UartTx]	values[9]	36	1			T34	1		T35	1		T36	2
auto[UartTx]	values[10]	24	1			T37	1		T395	1		T399	1
auto[UartRx]	values[0]	2276	1			T1	1		T2	21		T3	1
auto[UartRx]	values[1]	34	1			T36	1		T37	1		T40	2
auto[UartRx]	values[2]	35	1			T25	1		T27	2		T35	1
auto[UartRx]	values[3]	35	1			T25	1		T27	3		T40	2
auto[UartRx]	values[4]	27	1			T37	1		T397	1		T114	1
auto[UartRx]	values[5]	38	1			T27	1		T34	1		T38	1
auto[UartRx]	values[6]	42	1			T34	1		T183	2		T118	2
auto[UartRx]	values[7]	42	1			T26	1		T34	1		T36	2
auto[UartRx]	values[8]	42	1			T27	1		T36	1		T40	2
auto[UartRx]	values[9]	38	1			T35	1		T116	1		T400	1
auto[UartRx]	values[10]	41	1			T27	1		T39	1		T114	1