Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2541

1

T1

1

T2

1

T3

21

auto[UartRx]

2541

1

T1

1

T2

1

T3

21

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4393	1			T1	2		T2	2		T3	42
values[1]	36	1			T12	1		T21	1		T36	1
values[2]	60	1			T19	1		T21	1		T34	1
values[3]	57	1			T19	1		T35	1		T38	1
values[4]	67	1			T12	1		T21	2		T36	3
values[5]	51	1			T12	1		T35	2		T37	1
values[6]	63	1			T19	2		T21	2		T35	1
values[7]	60	1			T34	1		T38	1		T39	1
values[8]	84	1			T21	1		T35	3		T36	2
values[9]	73	1			T12	1		T34	1		T399	2
values[10]	88	1			T21	2		T34	1		T35	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2289	1			T1	1		T2	1		T3	21
auto[UartTx]	values[1]	14	1			T12	1		T36	1		T400	1
auto[UartTx]	values[2]	18	1			T34	1		T35	1		T36	1
auto[UartTx]	values[3]	21	1			T80	1		T267	2		T401	1
auto[UartTx]	values[4]	23	1			T36	1		T38	2		T311	1
auto[UartTx]	values[5]	24	1			T12	1		T311	2		T357	1
auto[UartTx]	values[6]	25	1			T19	1		T21	1		T35	1
auto[UartTx]	values[7]	20	1			T34	1		T38	1		T39	1
auto[UartTx]	values[8]	34	1			T21	1		T35	2		T36	1
auto[UartTx]	values[9]	27	1			T12	1		T399	1		T81	1
auto[UartTx]	values[10]	27	1			T34	1		T357	1		T267	1
auto[UartRx]	values[0]	2104	1			T1	1		T2	1		T3	21
auto[UartRx]	values[1]	22	1			T21	1		T311	2		T400	2
auto[UartRx]	values[2]	42	1			T19	1		T21	1		T35	2
auto[UartRx]	values[3]	36	1			T19	1		T35	1		T38	1
auto[UartRx]	values[4]	44	1			T12	1		T21	2		T36	2
auto[UartRx]	values[5]	27	1			T35	2		T37	1		T39	1
auto[UartRx]	values[6]	38	1			T19	1		T21	1		T40	1
auto[UartRx]	values[7]	40	1			T357	2		T372	1		T80	1
auto[UartRx]	values[8]	50	1			T35	1		T36	1		T37	1
auto[UartRx]	values[9]	46	1			T34	1		T399	1		T81	1
auto[UartRx]	values[10]	61	1			T21	2		T35	1		T36	1