Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2507	1			T5	1		T8	2		T9	8
auto[BaudRate115200]	2125	1			T6	1		T10	3		T14	1
auto[BaudRate230400]	2053	1			T4	1		T6	1		T10	3
auto[BaudRate128Kbps]	2118	1			T7	2		T10	3		T13	1
auto[BaudRate256Kbps]	2297	1			T3	2		T6	3		T10	6
auto[BaudRate1Mbps]	1927	1			T6	1		T7	2		T10	9
auto[BaudRate1p5Mbps]	1332	1			T4	1		T5	1		T7	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1947	1			T98	2		T17	2		T50	5
freqs[25]	1402	1			T12	4		T19	14		T131	8
freqs[48]	873	1			T3	2		T18	4		T401	8
freqs[50]	462	1			T14	2		T24	6		T289	5
freqs[100]	1140	1			T142	8		T321	2		T53	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	274	1			T132	1		T157	1		T174	1
auto[BaudRate9600]	freqs[25]	275	1			T19	14		T131	3		T402	10
auto[BaudRate9600]	freqs[48]	157	1			T401	8		T403	4		T41	1
auto[BaudRate9600]	freqs[50]	95	1			T24	3		T289	1		T404	3
auto[BaudRate9600]	freqs[100]	198	1			T142	1		T53	2		T301	1
auto[BaudRate115200]	freqs[24]	284	1			T98	1		T132	2		T157	2
auto[BaudRate115200]	freqs[25]	216	1			T12	1		T99	5		T137	3
auto[BaudRate115200]	freqs[48]	112	1			T18	1		T147	2		T41	2
auto[BaudRate115200]	freqs[50]	66	1			T14	1		T289	1		T404	3
auto[BaudRate115200]	freqs[100]	178	1			T142	1		T321	1		T53	2
auto[BaudRate230400]	freqs[24]	307	1			T17	1		T347	1		T132	1
auto[BaudRate230400]	freqs[25]	162	1			T12	3		T99	2		T137	1
auto[BaudRate230400]	freqs[48]	101	1			T305	1		T147	3		T160	2
auto[BaudRate230400]	freqs[50]	53	1			T24	3		T289	2		T404	6
auto[BaudRate230400]	freqs[100]	122	1			T142	1		T53	2		T145	1
auto[BaudRate128Kbps]	freqs[24]	338	1			T17	1		T347	1		T132	2
auto[BaudRate128Kbps]	freqs[25]	225	1			T131	2		T99	3		T405	18
auto[BaudRate128Kbps]	freqs[48]	128	1			T18	3		T305	3		T41	1
auto[BaudRate128Kbps]	freqs[50]	55	1			T289	1		T404	9		T309	1
auto[BaudRate128Kbps]	freqs[100]	149	1			T142	2		T321	1		T301	1
auto[BaudRate256Kbps]	freqs[24]	308	1			T98	1		T50	2		T132	2
auto[BaudRate256Kbps]	freqs[25]	236	1			T131	2		T99	4		T292	2
auto[BaudRate256Kbps]	freqs[48]	107	1			T3	2		T305	2		T41	3
auto[BaudRate256Kbps]	freqs[50]	53	1			T318	1		T309	1		T150	1
auto[BaudRate256Kbps]	freqs[100]	191	1			T142	1		T145	1		T331	1
auto[BaudRate1Mbps]	freqs[24]	293	1			T50	2		T174	1		T315	2
auto[BaudRate1Mbps]	freqs[25]	183	1			T131	1		T99	4		T292	2
auto[BaudRate1Mbps]	freqs[48]	148	1			T41	1		T160	1		T372	1
auto[BaudRate1Mbps]	freqs[50]	80	1			T14	1		T318	3		T404	9
auto[BaudRate1Mbps]	freqs[100]	165	1			T142	2		T164	1		T158	2
auto[BaudRate1p5Mbps]	freqs[25]	105	1			T99	1		T292	2		T405	6
auto[BaudRate1p5Mbps]	freqs[48]	120	1			T41	1		T383	1		T26	1
auto[BaudRate1p5Mbps]	freqs[50]	60	1			T318	1		T404	6		T309	2
auto[BaudRate1p5Mbps]	freqs[100]	137	1			T53	3		T145	2		T164	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded