Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1855	1			T1	1		T2	9		T4	1
auto[BaudRate115200]	1556	1			T2	9		T7	1		T8	1
auto[BaudRate230400]	1505	1			T1	1		T2	3		T7	4
auto[BaudRate128Kbps]	1526	1			T2	6		T8	1		T10	1
auto[BaudRate256Kbps]	1765	1			T2	9		T6	1		T7	1
auto[BaudRate1Mbps]	1528	1			T2	6		T4	1		T12	1
auto[BaudRate1p5Mbps]	1043	1			T2	3		T6	1		T11	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1126	1			T14	2		T11	5		T45	11
freqs[25]	1118	1			T2	45		T4	2		T263	8
freqs[48]	446	1			T402	17		T40	5		T403	2
freqs[50]	316	1			T7	6		T10	2		T29	10
freqs[100]	963	1			T88	7		T46	7		T279	20

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	162	1			T45	2		T275	1		T18	1
auto[BaudRate9600]	freqs[25]	139	1			T2	9		T4	1		T263	1
auto[BaudRate9600]	freqs[48]	105	1			T402	17		T404	1		T128	2
auto[BaudRate9600]	freqs[50]	61	1			T10	1		T29	2		T20	16
auto[BaudRate9600]	freqs[100]	151	1			T88	1		T46	1		T279	2
auto[BaudRate115200]	freqs[24]	163	1			T14	1		T11	1		T45	2
auto[BaudRate115200]	freqs[25]	155	1			T2	9		T405	9		T406	3
auto[BaudRate115200]	freqs[48]	65	1			T40	2		T307	2		T407	2
auto[BaudRate115200]	freqs[50]	49	1			T7	1		T29	2		T26	9
auto[BaudRate115200]	freqs[100]	136	1			T88	1		T46	2		T279	2
auto[BaudRate230400]	freqs[24]	171	1			T14	1		T11	1		T45	1
auto[BaudRate230400]	freqs[25]	138	1			T2	3		T263	2		T405	3
auto[BaudRate230400]	freqs[48]	57	1			T40	2		T307	3		T407	5
auto[BaudRate230400]	freqs[50]	49	1			T7	4		T26	6		T319	1
auto[BaudRate230400]	freqs[100]	115	1			T46	1		T279	1		T48	1
auto[BaudRate128Kbps]	freqs[24]	133	1			T11	1		T45	1		T275	2
auto[BaudRate128Kbps]	freqs[25]	146	1			T2	6		T263	2		T405	6
auto[BaudRate128Kbps]	freqs[48]	62	1			T307	2		T407	1		T408	1
auto[BaudRate128Kbps]	freqs[50]	44	1			T10	1		T26	3		T319	1
auto[BaudRate128Kbps]	freqs[100]	129	1			T88	1		T46	1		T279	2
auto[BaudRate256Kbps]	freqs[24]	188	1			T11	1		T45	2		T275	2
auto[BaudRate256Kbps]	freqs[25]	220	1			T2	9		T263	1		T269	3
auto[BaudRate256Kbps]	freqs[48]	46	1			T403	1		T407	1		T408	2
auto[BaudRate256Kbps]	freqs[50]	42	1			T7	1		T29	4		T26	3
auto[BaudRate256Kbps]	freqs[100]	145	1			T88	1		T279	3		T273	2
auto[BaudRate1Mbps]	freqs[24]	202	1			T45	2		T275	1		T18	2
auto[BaudRate1Mbps]	freqs[25]	195	1			T2	6		T4	1		T263	2
auto[BaudRate1Mbps]	freqs[48]	60	1			T307	2		T409	9		T407	2
auto[BaudRate1Mbps]	freqs[50]	31	1			T29	1		T319	1		T329	1
auto[BaudRate1Mbps]	freqs[100]	149	1			T88	1		T46	2		T279	6
auto[BaudRate1p5Mbps]	freqs[25]	125	1			T2	3		T269	3		T405	3
auto[BaudRate1p5Mbps]	freqs[48]	51	1			T40	1		T403	1		T307	1
auto[BaudRate1p5Mbps]	freqs[50]	40	1			T29	1		T329	2		T121	4
auto[BaudRate1p5Mbps]	freqs[100]	138	1			T88	2		T279	4		T273	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded