Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.95	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	6	124	95.38

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	6	124	95.38	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	21262669	1			T2	4		T7	34		T8	38
all_levels[1]	151676	1			T12	1		T29	14		T19	284
all_levels[2]	2132	1			T11	1		T29	9		T19	2
all_levels[3]	903	1			T29	4		T22	4		T28	1
all_levels[4]	647	1			T29	1		T22	3		T28	2
all_levels[5]	466	1			T12	1		T29	1		T22	2
all_levels[6]	355	1			T11	1		T22	5		T44	4
all_levels[7]	284	1			T22	1		T44	2		T45	1
all_levels[8]	243	1			T7	1		T12	1		T28	1
all_levels[9]	202	1			T22	1		T28	2		T44	2
all_levels[10]	169	1			T7	1		T29	1		T44	2
all_levels[11]	120	1			T22	2		T44	4		T46	1
all_levels[12]	132	1			T44	1		T104	2		T48	1
all_levels[13]	122	1			T22	1		T17	1		T105	1
all_levels[14]	104	1			T44	1		T46	1		T106	1
all_levels[15]	116	1			T7	2		T22	2		T46	1
all_levels[16]	86	1			T46	1		T48	2		T17	2
all_levels[17]	86	1			T22	1		T48	1		T17	1
all_levels[18]	82	1			T47	2		T21	1		T107	1
all_levels[19]	68	1			T48	1		T108	1		T107	2
all_levels[20]	67	1			T28	1		T44	1		T46	2
all_levels[21]	74	1			T11	1		T107	1		T109	2
all_levels[22]	51	1			T110	1		T93	1		T111	1
all_levels[23]	62	1			T22	1		T46	1		T93	1
all_levels[24]	42	1			T112	2		T113	1		T114	1
all_levels[25]	38	1			T88	1		T107	1		T110	1
all_levels[26]	44	1			T17	1		T18	1		T109	1
all_levels[27]	53	1			T46	2		T112	1		T115	1
all_levels[28]	31	1			T116	1		T117	1		T118	1
all_levels[29]	44	1			T106	1		T119	1		T120	1
all_levels[30]	42	1			T109	1		T119	1		T120	1
all_levels[31]	26	1			T120	1		T121	2		T122	1
all_levels[32]	28	1			T95	4		T93	2		T106	1
all_levels[33]	29	1			T115	1		T99	1		T123	1
all_levels[34]	22	1			T115	1		T121	1		T124	1
all_levels[35]	23	1			T11	1		T46	1		T95	2
all_levels[36]	29	1			T7	1		T125	1		T126	1
all_levels[37]	28	1			T18	1		T106	1		T125	1
all_levels[38]	27	1			T7	1		T109	1		T99	1
all_levels[39]	15	1			T119	1		T99	1		T124	1
all_levels[40]	16	1			T110	1		T127	2		T128	1
all_levels[41]	19	1			T99	1		T129	1		T130	1
all_levels[42]	15	1			T99	1		T114	1		T131	1
all_levels[43]	9	1			T125	1		T132	1		T133	1
all_levels[44]	9	1			T134	1		T135	1		T136	3
all_levels[45]	11	1			T115	1		T137	1		T138	1
all_levels[46]	24	1			T99	2		T139	1		T140	1
all_levels[47]	11	1			T134	1		T97	1		T141	1
all_levels[48]	19	1			T97	1		T142	1		T143	2
all_levels[49]	6	1			T115	1		T144	1		T145	1
all_levels[50]	16	1			T111	1		T122	1		T146	1
all_levels[51]	13	1			T11	2		T120	1		T114	1
all_levels[52]	4	1			T147	1		T148	1		T149	1
all_levels[53]	13	1			T99	1		T128	1		T150	1
all_levels[54]	11	1			T151	1		T148	1		T152	1
all_levels[55]	8	1			T153	1		T154	1		T155	1
all_levels[56]	6	1			T46	2		T95	1		T99	1
all_levels[57]	5	1			T156	1		T157	1		T158	1
all_levels[58]	10	1			T115	1		T159	1		T145	1
all_levels[59]	3	1			T21	1		T160	1		T161	1
all_levels[60]	6	1			T111	1		T162	2		T163	1
all_levels[61]	6	1			T164	1		T165	1		T166	1
all_levels[62]	7	1			T99	1		T167	1		T168	1
all_levels[63]	8	1			T164	1		T160	1		T146	1
all_levels[64]	100	1			T17	2		T18	1		T169	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21418053

1

T7

40

T8

38

T11

10

auto[1]

3739

1

T2

4

T9

1

T13

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	6	124	95.38	6

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[42] , all_levels[43]]	[auto[1]]	--	--	2
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[59]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	21259387	1			T7	34		T8	38		T11	5
all_levels[0]	auto[1]	3282	1			T2	4		T9	1		T13	1
all_levels[1]	auto[0]	151596	1			T12	1		T29	14		T19	284
all_levels[1]	auto[1]	80	1			T46	1		T170	1		T171	2
all_levels[2]	auto[0]	2110	1			T11	1		T29	9		T19	2
all_levels[2]	auto[1]	22	1			T17	1		T121	3		T132	1
all_levels[3]	auto[0]	883	1			T29	4		T22	4		T28	1
all_levels[3]	auto[1]	20	1			T121	3		T135	2		T172	1
all_levels[4]	auto[0]	619	1			T29	1		T22	3		T28	2
all_levels[4]	auto[1]	28	1			T170	2		T173	1		T174	1
all_levels[5]	auto[0]	450	1			T12	1		T29	1		T22	2
all_levels[5]	auto[1]	16	1			T175	2		T176	1		T177	1
all_levels[6]	auto[0]	339	1			T11	1		T22	5		T44	4
all_levels[6]	auto[1]	16	1			T170	1		T122	2		T143	2
all_levels[7]	auto[0]	273	1			T22	1		T44	2		T45	1
all_levels[7]	auto[1]	11	1			T97	1		T178	1		T179	5
all_levels[8]	auto[0]	227	1			T7	1		T12	1		T28	1
all_levels[8]	auto[1]	16	1			T180	1		T168	1		T181	1
all_levels[9]	auto[0]	188	1			T22	1		T28	2		T44	2
all_levels[9]	auto[1]	14	1			T182	1		T183	1		T174	1
all_levels[10]	auto[0]	154	1			T7	1		T29	1		T44	2
all_levels[10]	auto[1]	15	1			T184	1		T185	2		T186	1
all_levels[11]	auto[0]	111	1			T22	2		T44	4		T46	1
all_levels[11]	auto[1]	9	1			T187	1		T188	2		T189	3
all_levels[12]	auto[0]	125	1			T44	1		T104	2		T48	1
all_levels[12]	auto[1]	7	1			T17	1		T190	1		T191	2
all_levels[13]	auto[0]	111	1			T22	1		T17	1		T105	1
all_levels[13]	auto[1]	11	1			T192	2		T150	1		T193	1
all_levels[14]	auto[0]	95	1			T44	1		T46	1		T106	1
all_levels[14]	auto[1]	9	1			T85	2		T178	1		T194	2
all_levels[15]	auto[0]	104	1			T7	2		T22	2		T46	1
all_levels[15]	auto[1]	12	1			T173	1		T193	1		T195	1
all_levels[16]	auto[0]	83	1			T46	1		T48	2		T17	2
all_levels[16]	auto[1]	3	1			T196	1		T197	2		-	-
all_levels[17]	auto[0]	76	1			T22	1		T48	1		T17	1
all_levels[17]	auto[1]	10	1			T150	1		T198	1		T199	2
all_levels[18]	auto[0]	79	1			T47	2		T21	1		T107	1
all_levels[18]	auto[1]	3	1			T200	1		T201	1		T202	1
all_levels[19]	auto[0]	62	1			T48	1		T108	1		T107	2
all_levels[19]	auto[1]	6	1			T172	2		T203	2		T204	2
all_levels[20]	auto[0]	56	1			T28	1		T44	1		T46	1
all_levels[20]	auto[1]	11	1			T46	1		T119	1		T205	3
all_levels[21]	auto[0]	67	1			T11	1		T107	1		T109	2
all_levels[21]	auto[1]	7	1			T206	1		T207	1		T165	1
all_levels[22]	auto[0]	45	1			T110	1		T93	1		T111	1
all_levels[22]	auto[1]	6	1			T195	1		T208	1		T194	1
all_levels[23]	auto[0]	54	1			T22	1		T46	1		T93	1
all_levels[23]	auto[1]	8	1			T209	1		T210	2		T211	1
all_levels[24]	auto[0]	39	1			T112	2		T113	1		T114	1
all_levels[24]	auto[1]	3	1			T212	2		T213	1		-	-
all_levels[25]	auto[0]	31	1			T88	1		T107	1		T110	1
all_levels[25]	auto[1]	7	1			T214	3		T166	1		T215	2
all_levels[26]	auto[0]	40	1			T17	1		T18	1		T109	1
all_levels[26]	auto[1]	4	1			T212	1		T216	1		T217	1
all_levels[27]	auto[0]	47	1			T46	2		T112	1		T115	1
all_levels[27]	auto[1]	6	1			T218	3		T177	1		T166	1
all_levels[28]	auto[0]	29	1			T116	1		T117	1		T118	1
all_levels[28]	auto[1]	2	1			T219	2		-	-		-	-
all_levels[29]	auto[0]	38	1			T106	1		T119	1		T120	1
all_levels[29]	auto[1]	6	1			T220	2		T161	1		T221	1
all_levels[30]	auto[0]	40	1			T109	1		T119	1		T120	1
all_levels[30]	auto[1]	2	1			T222	2		-	-		-	-
all_levels[31]	auto[0]	24	1			T120	1		T121	2		T122	1
all_levels[31]	auto[1]	2	1			T223	1		T224	1		-	-
all_levels[32]	auto[0]	22	1			T95	2		T93	2		T106	1
all_levels[32]	auto[1]	6	1			T95	2		T113	1		T195	2
all_levels[33]	auto[0]	26	1			T115	1		T99	1		T123	1
all_levels[33]	auto[1]	3	1			T225	1		T226	1		T227	1
all_levels[34]	auto[0]	21	1			T115	1		T121	1		T124	1
all_levels[34]	auto[1]	1	1			T228	1		-	-		-	-
all_levels[35]	auto[0]	20	1			T11	1		T46	1		T95	1
all_levels[35]	auto[1]	3	1			T95	1		T229	1		T228	1
all_levels[36]	auto[0]	28	1			T7	1		T125	1		T126	1
all_levels[36]	auto[1]	1	1			T179	1		-	-		-	-
all_levels[37]	auto[0]	27	1			T18	1		T106	1		T125	1
all_levels[37]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[38]	auto[0]	25	1			T7	1		T109	1		T99	1
all_levels[38]	auto[1]	2	1			T231	2		-	-		-	-
all_levels[39]	auto[0]	14	1			T119	1		T99	1		T124	1
all_levels[39]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[40]	auto[0]	13	1			T110	1		T127	2		T128	1
all_levels[40]	auto[1]	3	1			T208	1		T233	2		-	-
all_levels[41]	auto[0]	13	1			T99	1		T129	1		T130	1
all_levels[41]	auto[1]	6	1			T234	4		T235	1		T236	1
all_levels[42]	auto[0]	15	1			T99	1		T114	1		T131	1
all_levels[43]	auto[0]	9	1			T125	1		T132	1		T133	1
all_levels[44]	auto[0]	7	1			T134	1		T135	1		T136	1
all_levels[44]	auto[1]	2	1			T136	2		-	-		-	-
all_levels[45]	auto[0]	11	1			T115	1		T137	1		T138	1
all_levels[46]	auto[0]	19	1			T99	2		T139	1		T140	1
all_levels[46]	auto[1]	5	1			T199	1		T237	1		T238	3
all_levels[47]	auto[0]	9	1			T134	1		T97	1		T141	1
all_levels[47]	auto[1]	2	1			T217	1		T239	1		-	-
all_levels[48]	auto[0]	11	1			T97	1		T142	1		T143	1
all_levels[48]	auto[1]	8	1			T143	1		T240	4		T241	1
all_levels[49]	auto[0]	5	1			T115	1		T144	1		T145	1
all_levels[49]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[50]	auto[0]	15	1			T111	1		T122	1		T146	1
all_levels[50]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[51]	auto[0]	11	1			T11	1		T120	1		T114	1
all_levels[51]	auto[1]	2	1			T11	1		T244	1		-	-
all_levels[52]	auto[0]	4	1			T147	1		T148	1		T149	1
all_levels[53]	auto[0]	8	1			T99	1		T128	1		T150	1
all_levels[53]	auto[1]	5	1			T245	1		T246	4		-	-
all_levels[54]	auto[0]	9	1			T151	1		T148	1		T152	1
all_levels[54]	auto[1]	2	1			T247	2		-	-		-	-
all_levels[55]	auto[0]	6	1			T153	1		T154	1		T155	1
all_levels[55]	auto[1]	2	1			T248	1		T249	1		-	-
all_levels[56]	auto[0]	5	1			T46	1		T95	1		T99	1
all_levels[56]	auto[1]	1	1			T46	1		-	-		-	-
all_levels[57]	auto[0]	5	1			T156	1		T157	1		T158	1
all_levels[58]	auto[0]	7	1			T115	1		T159	1		T145	1
all_levels[58]	auto[1]	3	1			T250	1		T251	1		T252	1
all_levels[59]	auto[0]	3	1			T21	1		T160	1		T161	1
all_levels[60]	auto[0]	5	1			T111	1		T162	2		T163	1
all_levels[60]	auto[1]	1	1			T253	1		-	-		-	-
all_levels[61]	auto[0]	5	1			T164	1		T165	1		T166	1
all_levels[61]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[62]	auto[0]	6	1			T99	1		T167	1		T168	1
all_levels[62]	auto[1]	1	1			T208	1		-	-		-	-
all_levels[63]	auto[0]	6	1			T164	1		T160	1		T146	1
all_levels[63]	auto[1]	2	1			T168	1		T255	1		-	-
all_levels[64]	auto[0]	81	1			T17	1		T18	1		T169	3
all_levels[64]	auto[1]	19	1			T17	1		T256	1		T257	2