Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_watermark_cg

Group : uart_env_pkg::uart_env_cov::rx_watermark_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_watermark_lvl	8	1	7	87.50	100	1	1	0

Summary for Variable cp_watermark_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for cp_watermark_lvl

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_levels[7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	1273	1			T19	13		T34	1		T91	6
all_levels[1]	454	1			T11	4		T48	8		T35	3
all_levels[2]	406	1			T46	5		T17	6		T92	2
all_levels[3]	263	1			T11	7		T16	4		T93	1
all_levels[4]	201	1			T46	2		T93	6		T94	1
all_levels[5]	79	1			T95	7		T96	2		T97	6
all_levels[6]	44	1			T98	6		T99	2		T100	4