Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	79300	1			T1	2		T2	1		T4	2
all_pins[1]	79300	1			T1	2		T2	1		T4	2
all_pins[2]	79300	1			T1	2		T2	1		T4	2
all_pins[3]	79300	1			T1	2		T2	1		T4	2
all_pins[4]	79300	1			T1	2		T2	1		T4	2
all_pins[5]	79300	1			T1	2		T2	1		T4	2
all_pins[6]	79300	1			T1	2		T2	1		T4	2
all_pins[7]	79300	1			T1	2		T2	1		T4	2
all_pins[8]	79300	1			T1	2		T2	1		T4	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	679624	1			T1	18		T2	8		T4	18
values[0x1]	34076	1			T2	1		T7	6		T8	3
transitions[0x0=>0x1]	27194	1			T2	1		T7	6		T8	3
transitions[0x1=>0x0]	26971	1			T7	6		T8	2		T9	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	63543	1			T1	2		T4	2		T6	2
all_pins[0]	values[0x1]	15757	1			T2	1		T8	2		T11	2
all_pins[0]	transitions[0x0=>0x1]	15334	1			T2	1		T8	2		T11	2
all_pins[0]	transitions[0x1=>0x0]	912	1			T11	4		T19	5		T16	4
all_pins[1]	values[0x0]	77965	1			T1	2		T2	1		T4	2
all_pins[1]	values[0x1]	1335	1			T11	4		T19	7		T16	4
all_pins[1]	transitions[0x0=>0x1]	1240	1			T11	4		T19	4		T16	4
all_pins[1]	transitions[0x1=>0x0]	1926	1			T7	4		T11	1		T29	2
all_pins[2]	values[0x0]	77279	1			T1	2		T2	1		T4	2
all_pins[2]	values[0x1]	2021	1			T7	4		T11	1		T29	2
all_pins[2]	transitions[0x0=>0x1]	1956	1			T7	4		T11	1		T29	2
all_pins[2]	transitions[0x1=>0x0]	208	1			T19	1		T16	2		T17	5
all_pins[3]	values[0x0]	79027	1			T1	2		T2	1		T4	2
all_pins[3]	values[0x1]	273	1			T19	3		T16	2		T17	5
all_pins[3]	transitions[0x0=>0x1]	238	1			T19	3		T16	2		T17	5
all_pins[3]	transitions[0x1=>0x0]	354	1			T19	7		T24	6		T258	10
all_pins[4]	values[0x0]	78911	1			T1	2		T2	1		T4	2
all_pins[4]	values[0x1]	389	1			T19	7		T24	6		T258	10
all_pins[4]	transitions[0x0=>0x1]	323	1			T19	5		T24	5		T258	10
all_pins[4]	transitions[0x1=>0x0]	116	1			T19	4		T16	1		T21	2
all_pins[5]	values[0x0]	79118	1			T1	2		T2	1		T4	2
all_pins[5]	values[0x1]	182	1			T19	6		T16	1		T21	2
all_pins[5]	transitions[0x0=>0x1]	143	1			T19	4		T16	1		T21	1
all_pins[5]	transitions[0x1=>0x0]	707	1			T19	6		T22	1		T28	1
all_pins[6]	values[0x0]	78554	1			T1	2		T2	1		T4	2
all_pins[6]	values[0x1]	746	1			T19	8		T22	1		T28	1
all_pins[6]	transitions[0x0=>0x1]	705	1			T19	5		T22	1		T28	1
all_pins[6]	transitions[0x1=>0x0]	274	1			T19	9		T16	2		T34	2
all_pins[7]	values[0x0]	78985	1			T1	2		T2	1		T4	2
all_pins[7]	values[0x1]	315	1			T19	12		T16	2		T34	2
all_pins[7]	transitions[0x0=>0x1]	170	1			T19	8		T109	3		T259	4
all_pins[7]	transitions[0x1=>0x0]	12913	1			T7	2		T8	1		T9	1
all_pins[8]	values[0x0]	66242	1			T1	2		T2	1		T4	2
all_pins[8]	values[0x1]	13058	1			T7	2		T8	1		T9	1
all_pins[8]	transitions[0x0=>0x1]	7085	1			T7	2		T8	1		T11	14
all_pins[8]	transitions[0x1=>0x0]	9561	1			T8	1		T11	1		T12	5