Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	126234	1			T3	2		T4	2		T5	2
all_pins[1]	126234	1			T3	2		T4	2		T5	2
all_pins[2]	126234	1			T3	2		T4	2		T5	2
all_pins[3]	126234	1			T3	2		T4	2		T5	2
all_pins[4]	126234	1			T3	2		T4	2		T5	2
all_pins[5]	126234	1			T3	2		T4	2		T5	2
all_pins[6]	126234	1			T3	2		T4	2		T5	2
all_pins[7]	126234	1			T3	2		T4	2		T5	2
all_pins[8]	126234	1			T3	2		T4	2		T5	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1091377	1			T3	18		T4	18		T5	18
values[0x1]	44729	1			T6	11		T7	7		T9	2
transitions[0x0=>0x1]	35811	1			T6	10		T7	7		T9	1
transitions[0x1=>0x0]	35629	1			T6	9		T7	6		T9	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	104581	1			T3	2		T4	2		T5	2
all_pins[0]	values[0x1]	21653	1			T6	3		T7	2		T9	1
all_pins[0]	transitions[0x0=>0x1]	21063	1			T6	3		T7	2		T9	1
all_pins[0]	transitions[0x1=>0x0]	1022	1			T6	7		T12	20		T17	10
all_pins[1]	values[0x0]	124622	1			T3	2		T4	2		T5	2
all_pins[1]	values[0x1]	1612	1			T6	7		T12	20		T17	10
all_pins[1]	transitions[0x0=>0x1]	1514	1			T6	6		T12	20		T17	10
all_pins[1]	transitions[0x1=>0x0]	2456	1			T7	1		T16	2		T28	2
all_pins[2]	values[0x0]	123680	1			T3	2		T4	2		T5	2
all_pins[2]	values[0x1]	2554	1			T6	1		T7	1		T16	2
all_pins[2]	transitions[0x0=>0x1]	2477	1			T6	1		T7	1		T16	2
all_pins[2]	transitions[0x1=>0x0]	260	1			T12	1		T148	1		T149	1
all_pins[3]	values[0x0]	125897	1			T3	2		T4	2		T5	2
all_pins[3]	values[0x1]	337	1			T12	1		T99	1		T148	3
all_pins[3]	transitions[0x0=>0x1]	290	1			T12	1		T148	3		T149	1
all_pins[3]	transitions[0x1=>0x0]	427	1			T12	12		T20	4		T99	2
all_pins[4]	values[0x0]	125760	1			T3	2		T4	2		T5	2
all_pins[4]	values[0x1]	474	1			T12	12		T20	4		T99	3
all_pins[4]	transitions[0x0=>0x1]	407	1			T12	12		T20	4		T99	3
all_pins[4]	transitions[0x1=>0x0]	183	1			T18	3		T99	1		T283	1
all_pins[5]	values[0x0]	125984	1			T3	2		T4	2		T5	2
all_pins[5]	values[0x1]	250	1			T18	3		T99	1		T101	1
all_pins[5]	transitions[0x0=>0x1]	201	1			T18	3		T99	1		T101	1
all_pins[5]	transitions[0x1=>0x0]	935	1			T12	2		T142	2		T29	4
all_pins[6]	values[0x0]	125250	1			T3	2		T4	2		T5	2
all_pins[6]	values[0x1]	984	1			T12	2		T142	2		T29	4
all_pins[6]	transitions[0x0=>0x1]	913	1			T12	2		T142	2		T29	4
all_pins[6]	transitions[0x1=>0x0]	275	1			T17	1		T18	1		T20	2
all_pins[7]	values[0x0]	125888	1			T3	2		T4	2		T5	2
all_pins[7]	values[0x1]	346	1			T17	1		T18	1		T20	2
all_pins[7]	transitions[0x0=>0x1]	187	1			T17	1		T20	2		T148	2
all_pins[7]	transitions[0x1=>0x0]	16360	1			T7	4		T9	1		T24	1
all_pins[8]	values[0x0]	109715	1			T3	2		T4	2		T5	2
all_pins[8]	values[0x1]	16519	1			T7	4		T9	1		T24	1
all_pins[8]	transitions[0x0=>0x1]	8759	1			T7	4		T12	55		T16	3
all_pins[8]	transitions[0x1=>0x0]	13711	1			T6	2		T7	1		T11	1