Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5563806	1			T7	7		T13	1		T11	13
all_levels[1]	910875	1			T7	2		T8	5		T12	3
all_levels[2]	181412	1			T8	3		T12	3		T29	1
all_levels[3]	212455	1			T12	3		T41	6		T29	22
all_levels[4]	157829	1			T12	3		T41	1059		T29	3
all_levels[5]	157947	1			T7	1		T12	2		T29	5
all_levels[6]	137894	1			T7	1		T12	2		T22	1
all_levels[7]	158866	1			T8	31		T12	4		T22	4
all_levels[8]	164904	1			T12	2		T22	1		T28	10
all_levels[9]	294936	1			T12	2		T29	1		T22	1
all_levels[10]	152026	1			T7	1		T12	2		T29	55
all_levels[11]	143669	1			T12	2		T29	1		T28	22
all_levels[12]	140962	1			T12	4		T28	6		T87	158
all_levels[13]	197787	1			T7	1		T12	2		T22	2
all_levels[14]	138742	1			T12	2		T28	3		T87	160
all_levels[15]	194331	1			T7	2		T12	2		T29	1
all_levels[16]	191081	1			T12	4		T19	1		T28	2
all_levels[17]	348820	1			T7	2		T12	2		T19	1
all_levels[18]	161268	1			T7	2		T12	2		T19	1
all_levels[19]	163751	1			T7	2		T12	3		T28	11
all_levels[20]	176771	1			T12	2		T28	1		T87	160
all_levels[21]	397494	1			T12	2		T87	160		T46	6
all_levels[22]	138313	1			T7	1		T12	2		T87	161
all_levels[23]	154488	1			T7	2		T12	2		T87	160
all_levels[24]	239205	1			T12	2		T87	160		T45	2
all_levels[25]	151510	1			T12	2		T87	164		T46	3
all_levels[26]	159709	1			T7	1		T12	2		T87	167
all_levels[27]	247036	1			T12	2		T29	46		T87	156
all_levels[28]	147243	1			T12	2		T19	1		T22	2
all_levels[29]	159630	1			T12	2		T87	157		T88	3
all_levels[30]	127089	1			T7	1		T12	247		T87	163
all_levels[31]	466945	1			T7	4		T12	587		T87	315
all_levels[32]	9082852	1			T7	10		T12	4457		T29	135

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21418053

1

T7

40

T8

38

T11

10

auto[1]

3593

1

T8

1

T13

1

T11

3

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5561711	1			T7	7		T11	10		T12	8
all_levels[0]	auto[1]	2095	1			T13	1		T11	3		T41	4
all_levels[1]	auto[0]	910651	1			T7	2		T8	5		T12	3
all_levels[1]	auto[1]	224	1			T46	2		T17	1		T106	2
all_levels[2]	auto[0]	181369	1			T8	3		T12	3		T29	1
all_levels[2]	auto[1]	43	1			T170	1		T364	1		T411	1
all_levels[3]	auto[0]	212363	1			T12	3		T41	1		T29	22
all_levels[3]	auto[1]	92	1			T41	5		T331	5		T391	27
all_levels[4]	auto[0]	157808	1			T12	3		T41	1059		T29	3
all_levels[4]	auto[1]	21	1			T359	1		T412	1		T413	1
all_levels[5]	auto[0]	157917	1			T7	1		T12	2		T29	5
all_levels[5]	auto[1]	30	1			T17	1		T170	1		T90	1
all_levels[6]	auto[0]	137877	1			T7	1		T12	2		T22	1
all_levels[6]	auto[1]	17	1			T414	1		T143	1		T415	4
all_levels[7]	auto[0]	158819	1			T8	30		T12	4		T22	4
all_levels[7]	auto[1]	47	1			T8	1		T100	5		T416	6
all_levels[8]	auto[0]	164883	1			T12	2		T22	1		T28	10
all_levels[8]	auto[1]	21	1			T262	1		T417	1		T418	1
all_levels[9]	auto[0]	294909	1			T12	2		T29	1		T22	1
all_levels[9]	auto[1]	27	1			T419	1		T367	3		T420	1
all_levels[10]	auto[0]	152006	1			T7	1		T12	2		T29	55
all_levels[10]	auto[1]	20	1			T44	1		T46	1		T263	1
all_levels[11]	auto[0]	143631	1			T12	2		T29	1		T28	22
all_levels[11]	auto[1]	38	1			T333	4		T421	1		T413	2
all_levels[12]	auto[0]	140949	1			T12	4		T28	6		T87	158
all_levels[12]	auto[1]	13	1			T105	1		T407	1		T367	1
all_levels[13]	auto[0]	197775	1			T7	1		T12	2		T22	2
all_levels[13]	auto[1]	12	1			T43	1		T275	1		T123	1
all_levels[14]	auto[0]	138716	1			T12	2		T28	3		T87	160
all_levels[14]	auto[1]	26	1			T17	1		T282	1		T365	1
all_levels[15]	auto[0]	194228	1			T7	2		T12	2		T29	1
all_levels[15]	auto[1]	103	1			T16	17		T24	7		T96	3
all_levels[16]	auto[0]	191060	1			T12	4		T19	1		T28	2
all_levels[16]	auto[1]	21	1			T95	1		T422	1		T390	1
all_levels[17]	auto[0]	348800	1			T7	2		T12	2		T19	1
all_levels[17]	auto[1]	20	1			T423	1		T132	1		T424	1
all_levels[18]	auto[0]	161244	1			T7	2		T12	2		T19	1
all_levels[18]	auto[1]	24	1			T279	1		T106	1		T314	1
all_levels[19]	auto[0]	163726	1			T7	2		T12	3		T28	11
all_levels[19]	auto[1]	25	1			T180	1		T424	1		T85	3
all_levels[20]	auto[0]	176744	1			T12	2		T28	1		T87	160
all_levels[20]	auto[1]	27	1			T46	1		T95	3		T97	1
all_levels[21]	auto[0]	397478	1			T12	2		T87	160		T46	6
all_levels[21]	auto[1]	16	1			T333	2		T285	1		T140	1
all_levels[22]	auto[0]	138295	1			T7	1		T12	2		T87	161
all_levels[22]	auto[1]	18	1			T263	1		T97	1		T412	1
all_levels[23]	auto[0]	154477	1			T7	2		T12	2		T87	160
all_levels[23]	auto[1]	11	1			T122	1		T425	1		T166	3
all_levels[24]	auto[0]	239193	1			T12	2		T87	160		T45	2
all_levels[24]	auto[1]	12	1			T106	1		T180	1		T426	1
all_levels[25]	auto[0]	151497	1			T12	2		T87	164		T46	3
all_levels[25]	auto[1]	13	1			T104	1		T427	1		T256	1
all_levels[26]	auto[0]	159682	1			T7	1		T12	2		T87	167
all_levels[26]	auto[1]	27	1			T306	1		T412	1		T428	1
all_levels[27]	auto[0]	247026	1			T12	2		T29	46		T87	156
all_levels[27]	auto[1]	10	1			T339	1		T429	2		T430	2
all_levels[28]	auto[0]	147224	1			T12	2		T19	1		T22	2
all_levels[28]	auto[1]	19	1			T413	1		T218	3		T184	1
all_levels[29]	auto[0]	159614	1			T12	2		T87	157		T88	3
all_levels[29]	auto[1]	16	1			T299	1		T431	1		T385	1
all_levels[30]	auto[0]	127082	1			T7	1		T12	247		T87	163
all_levels[30]	auto[1]	7	1			T147	1		T432	1		T177	1
all_levels[31]	auto[0]	466929	1			T7	4		T12	587		T87	315
all_levels[31]	auto[1]	16	1			T272	1		T304	1		T333	1
all_levels[32]	auto[0]	9082370	1			T7	10		T12	4457		T29	134
all_levels[32]	auto[1]	482	1			T29	1		T22	1		T43	4