Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7233929	1			T6	2		T7	10		T8	1
all_levels[1]	1858540	1			T6	5		T7	1		T11	3
all_levels[2]	475496	1			T7	1		T28	1		T142	9
all_levels[3]	261236	1			T11	2		T12	2		T29	24
all_levels[4]	332980	1			T12	151		T142	6		T29	14
all_levels[5]	315403	1			T11	3		T142	4		T29	9
all_levels[6]	314223	1			T102	1		T108	2		T142	2
all_levels[7]	264045	1			T12	10		T28	1		T17	9
all_levels[8]	819391	1			T12	156		T28	2		T102	2
all_levels[9]	391251	1			T7	3		T11	3		T142	23
all_levels[10]	250048	1			T11	1		T102	2		T142	17
all_levels[11]	249245	1			T142	28		T289	1		T29	7
all_levels[12]	252080	1			T16	1		T28	2		T102	2
all_levels[13]	332455	1			T7	1		T11	3		T142	18
all_levels[14]	266199	1			T102	6		T289	1		T29	74
all_levels[15]	299887	1			T16	1		T142	41		T289	4
all_levels[16]	434603	1			T11	3		T142	3		T289	2
all_levels[17]	234663	1			T102	1		T50	7		T51	34
all_levels[18]	613214	1			T102	1		T289	17		T29	1
all_levels[19]	290716	1			T11	1		T16	2		T289	1
all_levels[20]	508300	1			T11	1		T102	2		T289	3
all_levels[21]	223031	1			T11	2		T50	11		T133	3
all_levels[22]	498232	1			T16	2		T102	3		T289	3
all_levels[23]	344528	1			T289	9		T29	5		T50	11
all_levels[24]	312299	1			T11	1		T102	1		T50	7
all_levels[25]	215316	1			T7	1		T102	1		T50	9
all_levels[26]	338459	1			T11	2		T102	4		T50	6
all_levels[27]	215873	1			T50	7		T51	15		T157	2
all_levels[28]	533641	1			T102	1		T29	2		T50	8
all_levels[29]	244083	1			T102	6		T50	7		T51	83
all_levels[30]	184720	1			T11	3		T29	6		T50	9
all_levels[31]	1146471	1			T50	109		T52	4		T131	6
all_levels[32]	14052362	1			T7	13		T11	10		T16	9

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34302637

1

T6

2

T7

29

T11

47

auto[1]

4282

1

T6

5

T7

1

T8

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7231460	1			T7	10		T11	10		T12	4
all_levels[0]	auto[1]	2469	1			T6	2		T8	1		T12	26
all_levels[1]	auto[0]	1858220	1			T6	2		T7	1		T11	3
all_levels[1]	auto[1]	320	1			T6	3		T18	15		T146	3
all_levels[2]	auto[0]	475465	1			T7	1		T28	1		T142	9
all_levels[2]	auto[1]	31	1			T38	2		T203	1		T406	2
all_levels[3]	auto[0]	261159	1			T11	2		T12	1		T29	24
all_levels[3]	auto[1]	77	1			T12	1		T51	1		T101	1
all_levels[4]	auto[0]	332960	1			T12	151		T142	6		T29	14
all_levels[4]	auto[1]	20	1			T153	3		T103	1		T272	1
all_levels[5]	auto[0]	315357	1			T11	3		T142	4		T29	9
all_levels[5]	auto[1]	46	1			T174	1		T200	3		T35	1
all_levels[6]	auto[0]	314190	1			T102	1		T108	2		T142	2
all_levels[6]	auto[1]	33	1			T153	1		T160	1		T407	1
all_levels[7]	auto[0]	263901	1			T12	1		T28	1		T17	1
all_levels[7]	auto[1]	144	1			T12	9		T17	8		T160	1
all_levels[8]	auto[0]	819362	1			T12	156		T28	2		T102	2
all_levels[8]	auto[1]	29	1			T161	1		T120	1		T123	1
all_levels[9]	auto[0]	391224	1			T7	3		T11	3		T142	23
all_levels[9]	auto[1]	27	1			T144	1		T131	1		T205	3
all_levels[10]	auto[0]	250008	1			T11	1		T102	2		T142	17
all_levels[10]	auto[1]	40	1			T296	1		T369	1		T181	2
all_levels[11]	auto[0]	249218	1			T142	28		T289	1		T29	7
all_levels[11]	auto[1]	27	1			T306	1		T205	1		T139	1
all_levels[12]	auto[0]	252058	1			T16	1		T28	2		T102	2
all_levels[12]	auto[1]	22	1			T55	1		T155	1		T379	1
all_levels[13]	auto[0]	332420	1			T7	1		T11	3		T142	18
all_levels[13]	auto[1]	35	1			T148	1		T408	1		T235	1
all_levels[14]	auto[0]	266186	1			T102	6		T289	1		T29	74
all_levels[14]	auto[1]	13	1			T409	1		T64	1		T410	1
all_levels[15]	auto[0]	299777	1			T16	1		T142	41		T289	4
all_levels[15]	auto[1]	110	1			T20	7		T299	2		T135	9
all_levels[16]	auto[0]	434571	1			T11	3		T142	3		T289	2
all_levels[16]	auto[1]	32	1			T52	1		T42	1		T332	1
all_levels[17]	auto[0]	234646	1			T102	1		T50	7		T51	34
all_levels[17]	auto[1]	17	1			T161	1		T36	3		T411	1
all_levels[18]	auto[0]	613175	1			T102	1		T289	17		T29	1
all_levels[18]	auto[1]	39	1			T412	1		T169	1		T220	2
all_levels[19]	auto[0]	290701	1			T11	1		T16	2		T289	1
all_levels[19]	auto[1]	15	1			T413	2		T414	1		T201	1
all_levels[20]	auto[0]	508277	1			T11	1		T102	2		T289	3
all_levels[20]	auto[1]	23	1			T395	1		T415	1		T230	2
all_levels[21]	auto[0]	223010	1			T11	2		T50	11		T133	2
all_levels[21]	auto[1]	21	1			T133	1		T157	1		T314	1
all_levels[22]	auto[0]	498206	1			T16	1		T102	3		T289	3
all_levels[22]	auto[1]	26	1			T16	1		T390	1		T416	1
all_levels[23]	auto[0]	344509	1			T289	9		T29	5		T50	11
all_levels[23]	auto[1]	19	1			T182	1		T417	1		T418	1
all_levels[24]	auto[0]	312281	1			T11	1		T102	1		T50	7
all_levels[24]	auto[1]	18	1			T419	1		T420	1		T406	1
all_levels[25]	auto[0]	215304	1			T7	1		T102	1		T50	9
all_levels[25]	auto[1]	12	1			T421	1		T213	2		T422	1
all_levels[26]	auto[0]	338439	1			T11	2		T102	4		T50	6
all_levels[26]	auto[1]	20	1			T195	2		T423	1		T407	1
all_levels[27]	auto[0]	215860	1			T50	7		T51	15		T157	2
all_levels[27]	auto[1]	13	1			T367	1		T166	1		T424	1
all_levels[28]	auto[0]	533623	1			T102	1		T29	2		T50	8
all_levels[28]	auto[1]	18	1			T57	3		T181	1		T37	1
all_levels[29]	auto[0]	244063	1			T102	6		T50	7		T51	83
all_levels[29]	auto[1]	20	1			T182	1		T425	1		T244	1
all_levels[30]	auto[0]	184709	1			T11	3		T29	6		T50	9
all_levels[30]	auto[1]	11	1			T235	1		T36	1		T426	1
all_levels[31]	auto[0]	1146448	1			T50	109		T52	4		T131	6
all_levels[31]	auto[1]	23	1			T300	1		T387	1		T427	1
all_levels[32]	auto[0]	14051850	1			T7	12		T11	9		T16	5
all_levels[32]	auto[1]	512	1			T7	1		T11	1		T16	4