Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	683	1			T19	21		T21	7		T34	4
all_values[1]	683	1			T19	21		T21	7		T34	4
all_values[2]	683	1			T19	21		T21	7		T34	4
all_values[3]	683	1			T19	21		T21	7		T34	4
all_values[4]	683	1			T19	21		T21	7		T34	4
all_values[5]	683	1			T19	21		T21	7		T34	4
all_values[6]	683	1			T19	21		T21	7		T34	4
all_values[7]	683	1			T19	21		T21	7		T34	4
all_values[8]	683	1			T19	21		T21	7		T34	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3364

1

T19

92

T21

28

T34

18

auto[1]

2783

1

T19

97

T21

35

T34

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2003

1

T19

59

T21

24

T34

17

auto[1]

4144

1

T19

130

T21

39

T34

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3611

1

T19

109

T21

40

T34

27

auto[1]

2536

1

T19

80

T21

23

T34

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	223	1			T19	8		T21	1		T34	3
all_values[0]	auto[0]	auto[1]	auto[1]	184	1			T19	7		T21	3		T34	1
all_values[0]	auto[1]	auto[0]	auto[1]	149	1			T19	4		T39	6		T40	2
all_values[0]	auto[1]	auto[1]	auto[1]	127	1			T19	2		T21	3		T39	4
all_values[1]	auto[0]	auto[0]	auto[0]	242	1			T19	5		T21	4		T34	3
all_values[1]	auto[0]	auto[1]	auto[0]	155	1			T19	3		T21	3		T39	2
all_values[1]	auto[1]	auto[0]	auto[1]	161	1			T19	4		T34	1		T39	5
all_values[1]	auto[1]	auto[1]	auto[1]	125	1			T19	9		T39	6		T90	1
all_values[2]	auto[0]	auto[0]	auto[0]	140	1			T19	3		T34	3		T39	5
all_values[2]	auto[0]	auto[0]	auto[1]	74	1			T19	2		T21	1		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	129	1			T19	7		T21	1		T34	1
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T19	2		T21	2		T39	1
all_values[2]	auto[1]	auto[0]	auto[1]	135	1			T19	2		T21	2		T39	5
all_values[2]	auto[1]	auto[1]	auto[1]	136	1			T19	5		T21	1		T39	8
all_values[3]	auto[0]	auto[0]	auto[0]	174	1			T19	6		T34	1		T39	7
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T19	2		T21	1		T39	1
all_values[3]	auto[0]	auto[1]	auto[0]	106	1			T19	3		T21	1		T39	1
all_values[3]	auto[0]	auto[1]	auto[1]	58	1			T19	3		T34	1		T39	3
all_values[3]	auto[1]	auto[0]	auto[1]	159	1			T19	5		T21	4		T39	5
all_values[3]	auto[1]	auto[1]	auto[1]	122	1			T19	2		T21	1		T34	2
all_values[4]	auto[0]	auto[0]	auto[0]	141	1			T19	3		T34	3		T39	7
all_values[4]	auto[0]	auto[0]	auto[1]	68	1			T19	3		T40	1		T99	3
all_values[4]	auto[0]	auto[1]	auto[0]	129	1			T19	6		T21	2		T39	4
all_values[4]	auto[0]	auto[1]	auto[1]	59	1			T19	2		T21	1		T39	3
all_values[4]	auto[1]	auto[0]	auto[1]	148	1			T19	5		T21	3		T34	1
all_values[4]	auto[1]	auto[1]	auto[1]	138	1			T19	2		T21	1		T39	3
all_values[5]	auto[0]	auto[0]	auto[0]	131	1			T19	3		T21	2		T39	2
all_values[5]	auto[0]	auto[0]	auto[1]	68	1			T19	3		T39	3		T99	2
all_values[5]	auto[0]	auto[1]	auto[0]	124	1			T19	5		T34	2		T39	6
all_values[5]	auto[0]	auto[1]	auto[1]	63	1			T19	1		T21	2		T40	1
all_values[5]	auto[1]	auto[0]	auto[1]	172	1			T19	3		T21	2		T34	1
all_values[5]	auto[1]	auto[1]	auto[1]	125	1			T19	6		T21	1		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	142	1			T19	3		T34	2		T39	2
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T19	1		T39	4		T40	1
all_values[6]	auto[0]	auto[1]	auto[0]	131	1			T19	3		T21	4		T34	1
all_values[6]	auto[0]	auto[1]	auto[1]	60	1			T19	2		T21	1		T39	2
all_values[6]	auto[1]	auto[0]	auto[1]	146	1			T19	7		T21	1		T39	5
all_values[6]	auto[1]	auto[1]	auto[1]	134	1			T19	5		T21	1		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	146	1			T19	3		T21	5		T39	7
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T19	1		T40	1		T99	2
all_values[7]	auto[0]	auto[1]	auto[0]	113	1			T19	6		T21	2		T34	1
all_values[7]	auto[0]	auto[1]	auto[1]	64	1			T19	3		T34	1		T39	1
all_values[7]	auto[1]	auto[0]	auto[1]	165	1			T19	3		T39	5		T99	2
all_values[7]	auto[1]	auto[1]	auto[1]	118	1			T19	5		T34	2		T39	3
all_values[8]	auto[0]	auto[0]	auto[1]	223	1			T19	5		T21	2		T39	8
all_values[8]	auto[0]	auto[1]	auto[1]	184	1			T19	5		T21	2		T34	4
all_values[8]	auto[1]	auto[0]	auto[1]	146	1			T19	8		T39	4		T99	4
all_values[8]	auto[1]	auto[1]	auto[1]	130	1			T19	3		T21	3		T39	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal