Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	827	1			T99	4		T25	7		T100	8
all_values[1]	827	1			T99	4		T25	7		T100	8
all_values[2]	827	1			T99	4		T25	7		T100	8
all_values[3]	827	1			T99	4		T25	7		T100	8
all_values[4]	827	1			T99	4		T25	7		T100	8
all_values[5]	827	1			T99	4		T25	7		T100	8
all_values[6]	827	1			T99	4		T25	7		T100	8
all_values[7]	827	1			T99	4		T25	7		T100	8
all_values[8]	827	1			T99	4		T25	7		T100	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3941

1

T99

17

T25

28

T100

39

auto[1]

3502

1

T99

19

T25

35

T100

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2448

1

T99

10

T25

20

T100

21

auto[1]

4995

1

T99

26

T25

43

T100

51

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4352

1

T99

21

T25

36

T100

40

auto[1]

3091

1

T99

15

T25

27

T100

32

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	275	1			T99	2		T25	4		T100	1
all_values[0]	auto[0]	auto[1]	auto[1]	216	1			T99	1		T100	3		T27	1
all_values[0]	auto[1]	auto[0]	auto[1]	177	1			T25	1		T103	2		T27	2
all_values[0]	auto[1]	auto[1]	auto[1]	159	1			T99	1		T25	2		T100	4
all_values[1]	auto[0]	auto[0]	auto[0]	254	1			T99	1		T100	2		T103	2
all_values[1]	auto[0]	auto[1]	auto[0]	247	1			T99	1		T25	4		T100	1
all_values[1]	auto[1]	auto[0]	auto[1]	167	1			T25	2		T100	3		T27	1
all_values[1]	auto[1]	auto[1]	auto[1]	159	1			T99	2		T25	1		T100	2
all_values[2]	auto[0]	auto[0]	auto[0]	164	1			T100	2		T27	2		T34	2
all_values[2]	auto[0]	auto[0]	auto[1]	69	1			T99	1		T25	2		T138	1
all_values[2]	auto[0]	auto[1]	auto[0]	172	1			T99	1		T100	2		T103	1
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T25	1		T100	2		T27	1
all_values[2]	auto[1]	auto[0]	auto[1]	172	1			T99	1		T25	2		T103	3
all_values[2]	auto[1]	auto[1]	auto[1]	158	1			T99	1		T25	2		T100	2
all_values[3]	auto[0]	auto[0]	auto[0]	158	1			T25	1		T100	1		T27	4
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T99	1		T25	1		T100	1
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T25	2		T100	2		T138	3
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T99	1		T25	1		T34	2
all_values[3]	auto[1]	auto[0]	auto[1]	206	1			T99	2		T25	2		T100	2
all_values[3]	auto[1]	auto[1]	auto[1]	161	1			T100	2		T103	2		T27	1
all_values[4]	auto[0]	auto[0]	auto[0]	229	1			T25	2		T100	1		T103	2
all_values[4]	auto[0]	auto[0]	auto[1]	53	1			T100	1		T34	1		T129	3
all_values[4]	auto[0]	auto[1]	auto[0]	151	1			T99	1		T25	1		T100	3
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T99	1		T25	2		T138	4
all_values[4]	auto[1]	auto[0]	auto[1]	185	1			T100	3		T27	2		T34	4
all_values[4]	auto[1]	auto[1]	auto[1]	137	1			T99	2		T25	2		T103	2
all_values[5]	auto[0]	auto[0]	auto[0]	152	1			T25	2		T100	3		T34	3
all_values[5]	auto[0]	auto[0]	auto[1]	68	1			T99	1		T103	1		T138	1
all_values[5]	auto[0]	auto[1]	auto[0]	153	1			T25	3		T100	1		T103	1
all_values[5]	auto[0]	auto[1]	auto[1]	93	1			T100	1		T27	1		T138	1
all_values[5]	auto[1]	auto[0]	auto[1]	199	1			T99	3		T25	1		T100	1
all_values[5]	auto[1]	auto[1]	auto[1]	162	1			T25	1		T100	2		T103	1
all_values[6]	auto[0]	auto[0]	auto[0]	163	1			T99	1		T25	1		T100	1
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T100	1		T103	1		T139	1
all_values[6]	auto[0]	auto[1]	auto[0]	150	1			T99	1		T25	3		T100	2
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T99	1		T27	1		T34	3
all_values[6]	auto[1]	auto[0]	auto[1]	191	1			T25	1		T100	3		T103	2
all_values[6]	auto[1]	auto[1]	auto[1]	155	1			T99	1		T25	2		T100	1
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T99	1		T25	1		T103	1
all_values[7]	auto[0]	auto[0]	auto[1]	92	1			T25	1		T100	3		T27	2
all_values[7]	auto[0]	auto[1]	auto[0]	138	1			T99	3		T34	2		T138	3
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T25	1		T27	1		T36	1
all_values[7]	auto[1]	auto[0]	auto[1]	186	1			T25	3		T100	5		T103	3
all_values[7]	auto[1]	auto[1]	auto[1]	158	1			T25	1		T27	3		T34	1
all_values[8]	auto[0]	auto[0]	auto[1]	249	1			T99	2		T25	1		T100	3
all_values[8]	auto[0]	auto[1]	auto[1]	219	1			T25	2		T100	3		T103	1
all_values[8]	auto[1]	auto[0]	auto[1]	184	1			T99	1		T100	2		T103	2
all_values[8]	auto[1]	auto[1]	auto[1]	175	1			T99	1		T25	4		T27	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal