USBDEV Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: 50278df8b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.640s 2.443us 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.760s 32.376us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.100s 63.271us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.660s 398.470us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.400s 401.659us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.990s 161.372us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.100s 63.271us 20 20 100.00
usbdev_csr_aliasing 3.400s 401.659us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.430s 687.005us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.090s 173.511us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 intr_test usbdev_intr_test 0.700s 64.416us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.000s 257.068us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.000s 257.068us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.760s 32.376us 5 5 100.00
usbdev_csr_rw 1.100s 63.271us 20 20 100.00
usbdev_csr_aliasing 3.400s 401.659us 5 5 100.00
usbdev_same_csr_outstanding 10.780s 10.080ms 18 20 90.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.760s 32.376us 5 5 100.00
usbdev_csr_rw 1.100s 63.271us 20 20 100.00
usbdev_csr_aliasing 3.400s 401.659us 5 5 100.00
usbdev_same_csr_outstanding 10.780s 10.080ms 18 20 90.00
V2 TOTAL 88 90 97.78
V2S tl_intg_err usbdev_sec_cm 0.950s 124.763us 1 5 20.00
usbdev_tl_intg_err 11.150s 10.028ms 5 20 25.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 11.150s 10.028ms 5 20 25.00
V2S TOTAL 6 25 24.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.630s 2.211us 0 50 0.00
usbdev_stress_all 0.610s 0 50 0.00
TOTAL 159 330 48.18

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 3 3 2 66.67
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.36 90.13 74.16 95.23 0.00 86.90 92.01 96.10

Failure Buckets

Past Results