USBDEV Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.880s 252.513us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.940s 128.066us 5 5 100.00
V1 csr_rw usbdev_csr_rw 0.910s 154.743us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 7.990s 1.833ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 2.840s 129.075us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 1.990s 119.994us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 0.910s 154.743us 20 20 100.00
usbdev_csr_aliasing 2.840s 129.075us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.150s 719.092us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.030s 164.207us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.900s 274.030us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 3.100s 558.810us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 1.240s 87.484us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.670s 213.934us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.323m 20.729ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.530s 301.865us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.650s 217.138us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 2.100s 307.905us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.810s 253.876us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.470s 237.397us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.200s 221.564us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.630s 224.227us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.750s 270.750us 50 50 100.00
usbdev_stream_len_max 6.670s 1.397ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.970s 283.623us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.630s 218.064us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.600s 168.048us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.710s 188.874us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.910s 263.948us 50 50 100.00
V2 out_stall usbdev_out_stall 1.710s 245.800us 50 50 100.00
V2 in_stall usbdev_in_stall 1.600s 205.273us 50 50 100.00
V2 out_iso usbdev_out_iso 1.770s 259.651us 50 50 100.00
V2 in_iso usbdev_in_iso 2.250s 297.202us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.690s 194.318us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.850s 248.099us 50 50 100.00
V2 disconnected usbdev_disconnected 1.570s 206.640us 50 50 100.00
V2 host_lost usbdev_host_lost 16.640s 4.180ms 1 1 100.00
V2 link_reset usbdev_link_reset 1.460s 168.200us 1 1 100.00
V2 link_suspend usbdev_link_suspend 30.720s 10.432ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.215m 32.415ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.690s 183.835us 5 5 100.00
V2 rx_full usbdev_rx_full 2.560s 390.487us 50 50 100.00
V2 av_overflow usbdev_av_overflow 1.520s 207.503us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.840s 244.571us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.560s 174.247us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.790s 220.884us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.570s 191.598us 50 50 100.00
V2 link_out_err usbdev_link_out_err 2.380s 537.375us 1 1 100.00
V2 enable usbdev_enable 1.340s 129.812us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 59.090s 20.196ms 20 20 100.00
V2 device_address usbdev_device_address 1.845m 46.329ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 2.330s 528.700us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.680s 231.937us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 5.380s 1.085ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 4.630s 1.188ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 3.140s 681.328us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.630s 186.727us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.580s 213.226us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.900s 241.363us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.690s 213.382us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 2.130s 328.251us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.820s 229.694us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.690s 237.934us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.814m 4.007ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 5.097m 121.182ms 5 5 100.00
usbdev_freq_loclk 4.750m 110.100ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 4.235m 115.206ms 5 5 100.00
usbdev_freq_loclk_max 3.851m 99.171ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 4.958m 112.152ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.494m 3.796ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 2.189m 4.180ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 1.041m 5.690ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 1.012m 9.102ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.323m 20.729ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 2.150s 503.662us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 1.093m 31.060ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 56.710s 20.137ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 30.870s 10.868ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.938m 5.220ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 2.201m 3.987ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.557m 5.140ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 3.377m 7.772ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 4.849m 14.149ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 3.007m 9.598ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.640m 2.996ms 25 25 100.00
usbdev_max_usb_traffic 1.636m 2.871ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 4.010m 11.059ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.664m 13.028ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 5.890s 1.164ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 2.560s 404.312us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 4.090s 313.891us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 1.092m 492 500 98.40
V2 intr_test usbdev_intr_test 0.830s 112.883us 50 50 100.00
V2 alert_test usbdev_alert_test 1.250s 116.749us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.330s 305.146us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.330s 305.146us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.940s 128.066us 5 5 100.00
usbdev_csr_rw 0.910s 154.743us 20 20 100.00
usbdev_csr_aliasing 2.840s 129.075us 5 5 100.00
usbdev_same_csr_outstanding 1.630s 335.883us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.940s 128.066us 5 5 100.00
usbdev_csr_rw 0.910s 154.743us 20 20 100.00
usbdev_csr_aliasing 2.840s 129.075us 5 5 100.00
usbdev_same_csr_outstanding 1.630s 335.883us 20 20 100.00
V2 TOTAL 3591 3599 99.78
V2S tl_intg_err usbdev_sec_cm 3.350s 881.295us 5 5 100.00
usbdev_tl_intg_err 5.720s 1.730ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.720s 1.730ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 2.826m 5.106ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 1.070s 54.644us 0 10 0.00
usbdev_stress_all 0.870s 0 50 0.00
TOTAL 3732 3800 98.21

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 84 98.82
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.44 98.11 95.91 97.44 87.30 98.22 98.17 92.94

Failure Buckets

Past Results