USBDEV Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 9.190s 10.006ms 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.800s 34.537us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.090s 179.314us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 10.350s 1.779ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.530s 301.441us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 4.810s 274.217us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.090s 179.314us 20 20 100.00
usbdev_csr_aliasing 3.530s 301.441us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.210s 470.262us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.250s 145.857us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 intr_test usbdev_intr_test 0.690s 126.194us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 8.210s 10.016ms 19 20 95.00
V2 tl_d_illegal_access usbdev_tl_errors 8.210s 10.016ms 19 20 95.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.800s 34.537us 5 5 100.00
usbdev_csr_rw 1.090s 179.314us 20 20 100.00
usbdev_csr_aliasing 3.530s 301.441us 5 5 100.00
usbdev_same_csr_outstanding 9.440s 10.123ms 18 20 90.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.800s 34.537us 5 5 100.00
usbdev_csr_rw 1.090s 179.314us 20 20 100.00
usbdev_csr_aliasing 3.530s 301.441us 5 5 100.00
usbdev_same_csr_outstanding 9.440s 10.123ms 18 20 90.00
V2 TOTAL 87 90 96.67
V2S tl_intg_err usbdev_sec_cm 10.110s 10.004ms 1 5 20.00
usbdev_tl_intg_err 10.450s 10.007ms 4 20 20.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 10.450s 10.007ms 4 20 20.00
V2S TOTAL 5 25 20.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.620s 1.945us 0 50 0.00
usbdev_stress_all 0.580s 0 50 0.00
TOTAL 157 330 47.58

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 3 3 1 33.33
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.30 90.13 74.16 95.01 0.00 86.90 92.01 95.91

Failure Buckets

Past Results