USBDEV Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.620s 5.935us 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.840s 50.268us 5 5 100.00
V1 csr_rw usbdev_csr_rw 0.970s 59.455us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 10.050s 1.185ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.570s 313.868us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 1.360s 56.976us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 0.970s 59.455us 20 20 100.00
usbdev_csr_aliasing 3.570s 313.868us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.470s 472.865us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.370s 157.120us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 intr_test usbdev_intr_test 0.720s 30.310us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.000s 230.119us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.000s 230.119us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.840s 50.268us 5 5 100.00
usbdev_csr_rw 0.970s 59.455us 20 20 100.00
usbdev_csr_aliasing 3.570s 313.868us 5 5 100.00
usbdev_same_csr_outstanding 1.470s 109.767us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.840s 50.268us 5 5 100.00
usbdev_csr_rw 0.970s 59.455us 20 20 100.00
usbdev_csr_aliasing 3.570s 313.868us 5 5 100.00
usbdev_same_csr_outstanding 1.470s 109.767us 20 20 100.00
V2 TOTAL 90 90 100.00
V2S tl_intg_err usbdev_sec_cm 1.010s 162.058us 5 5 100.00
usbdev_tl_intg_err 5.380s 541.364us 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.380s 541.364us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.610s 5.887us 0 50 0.00
usbdev_stress_all 0.580s 0 50 0.00
TOTAL 180 330 54.55

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 3 3 3 100.00
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
72.70 89.73 73.67 91.76 0.00 86.85 89.96 76.95

Failure Buckets

Past Results