USBDEV Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.970s 301.629us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.980s 173.296us 5 5 100.00
V1 csr_rw usbdev_csr_rw 0.980s 90.778us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 6.490s 712.859us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.000s 359.275us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.070s 125.666us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 0.980s 90.778us 20 20 100.00
usbdev_csr_aliasing 3.000s 359.275us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.440s 233.352us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 1.970s 166.600us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.810s 215.957us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 3.050s 499.076us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 1.230s 96.690us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.620s 201.000us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.049m 22.584ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 2.250s 330.213us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.600s 188.050us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.890s 291.647us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.700s 212.983us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.770s 236.926us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.710s 223.945us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.550s 203.780us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.740s 207.356us 50 50 100.00
usbdev_stream_len_max 5.630s 1.321ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.840s 259.408us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.530s 207.792us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.650s 214.681us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.640s 181.967us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.780s 229.455us 50 50 100.00
V2 out_stall usbdev_out_stall 1.600s 218.751us 50 50 100.00
V2 in_stall usbdev_in_stall 1.580s 178.891us 50 50 100.00
V2 out_iso usbdev_out_iso 1.730s 276.388us 50 50 100.00
V2 in_iso usbdev_in_iso 2.170s 232.392us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.640s 199.224us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.730s 238.244us 50 50 100.00
V2 disconnected usbdev_disconnected 1.640s 226.352us 50 50 100.00
V2 host_lost usbdev_host_lost 16.320s 4.169ms 1 1 100.00
V2 link_reset usbdev_link_reset 1.470s 169.162us 1 1 100.00
V2 link_suspend usbdev_link_suspend 27.830s 9.526ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.352m 27.641ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.570s 197.046us 5 5 100.00
V2 rx_full usbdev_rx_full 2.400s 423.789us 50 50 100.00
V2 av_overflow usbdev_av_overflow 1.490s 149.535us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.700s 256.904us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.620s 234.551us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.580s 163.632us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.580s 222.206us 50 50 100.00
V2 link_out_err usbdev_link_out_err 2.310s 439.753us 1 1 100.00
V2 enable usbdev_enable 1.380s 137.712us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 47.600s 20.153ms 20 20 100.00
V2 device_address usbdev_device_address 2.117m 42.535ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 2.300s 509.099us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.620s 215.411us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 5.150s 960.364us 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 5.320s 1.217ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 1.036m 183 200 91.50
V2 out_trans_nak usbdev_out_trans_nak 1.730s 246.010us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.550s 191.768us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.840s 277.880us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.620s 220.175us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.720s 206.972us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.670s 196.040us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.540s 180.536us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.837m 3.954ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 4.198m 120.204ms 5 5 100.00
usbdev_freq_loclk 3.521m 108.112ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.885m 120.096ms 5 5 100.00
usbdev_freq_loclk_max 4.027m 117.147ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.434m 120.168ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.815m 4.150ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.822m 3.930ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 49.120s 2.053ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 46.870s 5.719ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.049m 22.584ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 2.520s 453.304us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 1.347m 29.512ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 46.700s 16.401ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 27.110s 9.841ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.441m 5.461ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.559m 3.209ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.217m 4.670ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 6.438m 18.745ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.333m 11.226ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 1.959m 17.810ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.518m 3.452ms 25 25 100.00
usbdev_max_usb_traffic 1.612m 3.538ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 4.572m 10.678ms 10 10 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.539m 12.969ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 5.070s 1.154ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 2.820s 431.747us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 4.420s 479.991us 50 50 100.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 46.005s 430 500 86.00
V2 fifo_levels usbdev_fifo_levels 1.036m 150 160 93.75
V2 intr_test usbdev_intr_test 0.790s 128.402us 50 50 100.00
V2 alert_test usbdev_alert_test 1.230s 101.345us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.130s 289.212us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.130s 289.212us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.980s 173.296us 5 5 100.00
usbdev_csr_rw 0.980s 90.778us 20 20 100.00
usbdev_csr_aliasing 3.000s 359.275us 5 5 100.00
usbdev_same_csr_outstanding 1.600s 156.983us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.980s 173.296us 5 5 100.00
usbdev_csr_rw 0.980s 90.778us 20 20 100.00
usbdev_csr_aliasing 3.000s 359.275us 5 5 100.00
usbdev_same_csr_outstanding 1.600s 156.983us 20 20 100.00
V2 TOTAL 3667 3764 97.42
V2S tl_intg_err usbdev_sec_cm 2.810s 1.308ms 5 5 100.00
usbdev_tl_intg_err 4.660s 1.412ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 4.660s 1.412ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 2.467m 5.121ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 1.040s 40.078us 0 10 0.00
usbdev_stress_all 0.890s 0 50 0.00
TOTAL 3808 3965 96.04

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 86 86 83 96.51
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.36 98.21 96.00 97.44 94.92 98.38 98.21 98.37

Failure Buckets

Past Results