Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	286	1		T31	5		T11	2		T12	2
all_values[1]	286	1		T31	5		T11	2		T12	2
all_values[2]	286	1		T31	5		T11	2		T12	2
all_values[3]	286	1		T31	5		T11	2		T12	2
all_values[4]	286	1		T31	5		T11	2		T12	2
all_values[5]	286	1		T31	5		T11	2		T12	2
all_values[6]	286	1		T31	5		T11	2		T12	2
all_values[7]	286	1		T31	5		T11	2		T12	2
all_values[8]	286	1		T31	5		T11	2		T12	2
all_values[9]	286	1		T31	5		T11	2		T12	2
all_values[10]	286	1		T31	5		T11	2		T12	2
all_values[11]	286	1		T31	5		T11	2		T12	2
all_values[12]	286	1		T31	5		T11	2		T12	2
all_values[13]	286	1		T31	5		T11	2		T12	2
all_values[14]	286	1		T31	5		T11	2		T12	2
all_values[15]	286	1		T31	5		T11	2		T12	2
all_values[16]	286	1		T31	5		T11	2		T12	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2724	1		T31	44		T11	34		T12	34
auto[1]	2138	1		T31	41		T32	59		T22	49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1343	1		T31	21		T11	34		T12	34
auto[1]	3519	1		T31	64		T32	117		T22	49

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	53	1		T31	1		T11	2		T12	2
all_values[0]	auto[0]	auto[1]	90	1		T31	3		T32	5		T33	1
all_values[0]	auto[1]	auto[0]	32	1		T31	1		T22	5		T33	1
all_values[0]	auto[1]	auto[1]	111	1		T32	3		T33	3		T34	1
all_values[1]	auto[0]	auto[0]	55	1		T11	2		T12	2		T32	1
all_values[1]	auto[0]	auto[1]	96	1		T31	1		T32	4		T22	1
all_values[1]	auto[1]	auto[0]	30	1		T32	2		T33	1		T34	1
all_values[1]	auto[1]	auto[1]	105	1		T31	4		T32	1		T22	4
all_values[2]	auto[0]	auto[0]	47	1		T11	2		T12	2		T17	2
all_values[2]	auto[0]	auto[1]	128	1		T31	5		T32	5		T22	3
all_values[2]	auto[1]	auto[0]	24	1		T22	1		T33	2		T78	2
all_values[2]	auto[1]	auto[1]	87	1		T32	3		T22	1		T33	3
all_values[3]	auto[0]	auto[0]	60	1		T11	2		T12	2		T32	6
all_values[3]	auto[0]	auto[1]	104	1		T31	3		T22	1		T33	3
all_values[3]	auto[1]	auto[0]	13	1		T31	1		T32	2		T78	1
all_values[3]	auto[1]	auto[1]	109	1		T31	1		T22	4		T33	1
all_values[4]	auto[0]	auto[0]	52	1		T31	2		T11	2		T12	2
all_values[4]	auto[0]	auto[1]	102	1		T32	5		T33	4		T34	2
all_values[4]	auto[1]	auto[0]	33	1		T22	4		T33	1		T47	1
all_values[4]	auto[1]	auto[1]	99	1		T31	3		T32	3		T34	6
all_values[5]	auto[0]	auto[0]	53	1		T31	1		T11	2		T12	2
all_values[5]	auto[0]	auto[1]	107	1		T31	3		T32	3		T22	1
all_values[5]	auto[1]	auto[0]	9	1		T31	1		T71	1		T79	2
all_values[5]	auto[1]	auto[1]	117	1		T32	5		T22	4		T33	4
all_values[6]	auto[0]	auto[0]	59	1		T11	2		T12	2		T17	2
all_values[6]	auto[0]	auto[1]	105	1		T31	5		T32	2		T22	2
all_values[6]	auto[1]	auto[0]	20	1		T34	1		T47	3		T78	2
all_values[6]	auto[1]	auto[1]	102	1		T32	6		T22	3		T33	3
all_values[7]	auto[0]	auto[0]	57	1		T11	2		T12	2		T17	2
all_values[7]	auto[0]	auto[1]	98	1		T31	4		T32	6		T22	4
all_values[7]	auto[1]	auto[0]	20	1		T34	2		T78	2		T72	1
all_values[7]	auto[1]	auto[1]	111	1		T31	1		T32	2		T33	3
all_values[8]	auto[0]	auto[0]	43	1		T11	2		T12	2		T17	2
all_values[8]	auto[0]	auto[1]	104	1		T32	3		T33	4		T34	1
all_values[8]	auto[1]	auto[0]	33	1		T31	2		T22	5		T34	1
all_values[8]	auto[1]	auto[1]	106	1		T31	3		T32	5		T33	1
all_values[9]	auto[0]	auto[0]	59	1		T11	2		T12	2		T17	2
all_values[9]	auto[0]	auto[1]	91	1		T32	6		T22	4		T33	3
all_values[9]	auto[1]	auto[0]	24	1		T31	1		T32	1		T34	1
all_values[9]	auto[1]	auto[1]	112	1		T31	4		T32	1		T33	1
all_values[10]	auto[0]	auto[0]	61	1		T31	3		T11	2		T12	2
all_values[10]	auto[0]	auto[1]	107	1		T32	5		T22	4		T34	3
all_values[10]	auto[1]	auto[0]	24	1		T31	2		T47	1		T71	2
all_values[10]	auto[1]	auto[1]	94	1		T32	2		T33	4		T34	5
all_values[11]	auto[0]	auto[0]	72	1		T11	2		T12	2		T32	1
all_values[11]	auto[0]	auto[1]	95	1		T32	3		T33	3		T34	1
all_values[11]	auto[1]	auto[0]	20	1		T31	1		T33	1		T78	2
all_values[11]	auto[1]	auto[1]	99	1		T31	4		T32	4		T34	7
all_values[12]	auto[0]	auto[0]	58	1		T11	2		T12	2		T17	2
all_values[12]	auto[0]	auto[1]	105	1		T31	3		T32	2		T34	6
all_values[12]	auto[1]	auto[0]	20	1		T32	2		T78	1		T71	4
all_values[12]	auto[1]	auto[1]	103	1		T31	2		T32	4		T22	5
all_values[13]	auto[0]	auto[0]	53	1		T11	2		T12	2		T17	2
all_values[13]	auto[0]	auto[1]	113	1		T31	2		T32	4		T34	4
all_values[13]	auto[1]	auto[0]	12	1		T32	1		T80	1		T72	2
all_values[13]	auto[1]	auto[1]	108	1		T31	3		T32	3		T22	4
all_values[14]	auto[0]	auto[0]	72	1		T31	2		T11	2		T12	2
all_values[14]	auto[0]	auto[1]	117	1		T32	4		T34	6		T47	4
all_values[14]	auto[1]	auto[0]	19	1		T31	3		T32	1		T81	3
all_values[14]	auto[1]	auto[1]	78	1		T32	2		T33	4		T34	2
all_values[15]	auto[0]	auto[0]	60	1		T11	2		T12	2		T17	2
all_values[15]	auto[0]	auto[1]	100	1		T31	2		T32	4		T34	8
all_values[15]	auto[1]	auto[0]	16	1		T22	1		T33	2		T82	4
all_values[15]	auto[1]	auto[1]	110	1		T31	3		T32	4		T22	4
all_values[16]	auto[0]	auto[0]	55	1		T11	2		T12	2		T17	2
all_values[16]	auto[0]	auto[1]	93	1		T31	4		T32	6		T33	3
all_values[16]	auto[1]	auto[0]	25	1		T22	4		T34	1		T83	1
all_values[16]	auto[1]	auto[1]	113	1		T31	1		T32	2		T34	2