Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.09	90.01	75.82	95.05	3.12	87.16	92.01	96.47

Total tests in report: 152

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
54.95	54.95	67.16	67.16	60.13	60.13	79.57	79.57	0.00	0.00	73.58	73.58	67.62	67.62	36.62	36.62	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2398169677
66.28	11.32	88.94	21.77	71.37	11.23	88.82	9.25	3.12	3.12	86.81	13.23	87.91	20.29	36.99	0.37	/workspace/coverage/default/4.usbdev_sec_cm.4179985437
73.25	6.97	90.05	1.11	72.93	1.56	91.83	3.01	3.12	0.00	86.81	0.00	87.91	0.00	80.11	43.12	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.2457587777
74.50	1.25	90.05	0.00	72.93	0.00	92.04	0.22	3.12	0.00	86.81	0.00	87.91	0.00	88.66	8.55	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2045443124
75.18	0.67	90.09	0.04	74.13	1.20	92.04	0.00	3.12	0.00	86.90	0.09	88.32	0.41	91.64	2.97	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1942352272
75.75	0.57	90.09	0.00	74.13	0.00	94.19	2.15	3.12	0.00	86.90	0.00	90.16	1.84	91.64	0.00	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3166776437
76.06	0.31	90.11	0.02	75.23	1.10	95.05	0.86	3.12	0.00	87.11	0.22	90.16	0.00	91.64	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.214799093
76.33	0.27	90.11	0.00	75.26	0.03	95.05	0.00	3.12	0.00	87.11	0.00	90.16	0.00	93.49	1.86	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.2072415439
76.59	0.26	90.11	0.00	75.26	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	1.84	93.49	0.00	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2862003088
76.75	0.16	90.11	0.00	75.26	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	94.61	1.12	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1135238424
76.83	0.08	90.11	0.00	75.26	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	95.17	0.56	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2119550486
76.91	0.08	90.11	0.00	75.26	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	95.72	0.56	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1029834021
76.97	0.05	90.11	0.00	75.26	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.10	0.37	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3552453359
77.00	0.04	90.28	0.17	75.36	0.10	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.10	0.00	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.575782724
77.04	0.04	90.28	0.00	75.44	0.08	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.28	0.19	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2766799919
77.07	0.03	90.28	0.00	75.44	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.19	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1900429034
77.09	0.02	90.28	0.00	75.59	0.15	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.987509980
77.11	0.02	90.38	0.10	75.59	0.00	95.05	0.00	3.12	0.00	87.16	0.04	92.01	0.00	96.47	0.00	/workspace/coverage/default/2.usbdev_sec_cm.814549922
77.13	0.02	90.38	0.00	75.72	0.13	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3991610898
77.14	0.01	90.38	0.00	75.79	0.08	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1815411682
77.14	0.01	90.38	0.00	75.82	0.03	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/default/1.usbdev_sec_cm.1365330994

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.873044692
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4284397056
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2662247201
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.634672506
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2096441321
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.565949440
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1541009686
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2890787898
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2401783860
/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1108535915
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1476767128
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.915992803
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2678092990
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1453424908
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4126451340
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.480386911
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.443844345
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3421611803
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3121365826
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.881777902
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.46308610
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3977260195
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.673446117
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3069428563
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3517186855
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1250915282
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.843157489
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2808683823
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2137929589
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2733955132
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.4006174492
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1261475009
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3659333500
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2970240195
/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3402064799
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.565010056
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2618069305
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.1370967571
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3463886430
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1167945138
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2202648171
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1983708910
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3614729584
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3741969514
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.255106720
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3333767203
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2470878713
/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1690430242
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1640701381
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.368875165
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1641620124
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3403639939
/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3354967845
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1184741603
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1727142146
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.1596344460
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3389955497
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3358677411
/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.9284447
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2069438511
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1324293043
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1821412618
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3581405909
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.314413236
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.892490638
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1544143066
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2961313313
/workspace/coverage/cover_reg_top/20.usbdev_intr_test.125155042
/workspace/coverage/cover_reg_top/21.usbdev_intr_test.2077744621
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2982064376
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.2363197626
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.2337112960
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1514103651
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.2450715049
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4239734569
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3301432942
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.250918635
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3494680961
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3576126555
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.430068136
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.766525314
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4121989680
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2689953763
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.2884352276
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3532460774
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3920797232
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2032527163
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.2840457919
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.486752584
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1153490001
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1208507170
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4245312082
/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3046498067
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.539805942
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4201363384
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4028744974
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1571952348
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.4156645822
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.384616639
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.2170558958
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2851085260
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3050938976
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2673346113
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3403002654
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2755353377
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2700593311
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3220024373
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1009524160
/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1545263035
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3198328657
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.143467615
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1991962245
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4281971439
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.769115136
/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2774410356
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3941108950
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3368352750
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1771074619
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4050872
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.158363252
/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2099265591
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3773673366
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.299746217
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2943711668
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.893012501
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2859475145
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2677124671
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.602505978
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1102829391
/workspace/coverage/default/0.usbdev_sec_cm.1748648281
/workspace/coverage/default/3.usbdev_sec_cm.1290740021

Total test records in report: 152

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.usbdev_sec_cm.1365330994	Jan 03 12:27:59 PM PST 24	Jan 03 12:28:10 PM PST 24	167127108 ps
T2	/workspace/coverage/default/2.usbdev_sec_cm.814549922	Jan 03 12:25:33 PM PST 24	Jan 03 12:25:35 PM PST 24	174273827 ps
T3	/workspace/coverage/default/4.usbdev_sec_cm.4179985437	Jan 03 12:27:59 PM PST 24	Jan 03 12:28:10 PM PST 24	156754151 ps
T4	/workspace/coverage/default/0.usbdev_sec_cm.1748648281	Jan 03 12:30:01 PM PST 24	Jan 03 12:30:47 PM PST 24	180244861 ps
T5	/workspace/coverage/default/3.usbdev_sec_cm.1290740021	Jan 03 12:25:31 PM PST 24	Jan 03 12:25:33 PM PST 24	182816994 ps
T6	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.881777902	Jan 03 12:29:30 PM PST 24	Jan 03 12:30:04 PM PST 24	64475921 ps
T7	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4239734569	Jan 03 12:30:49 PM PST 24	Jan 03 12:31:58 PM PST 24	327463055 ps
T8	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2398169677	Jan 03 12:25:22 PM PST 24	Jan 03 12:25:29 PM PST 24	255935049 ps
T9	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.143467615	Jan 03 12:30:07 PM PST 24	Jan 03 12:30:54 PM PST 24	38997105 ps
T10	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3333767203	Jan 03 12:36:01 PM PST 24	Jan 03 12:37:41 PM PST 24	76109133 ps
T31	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1983708910	Jan 03 12:25:05 PM PST 24	Jan 03 12:25:10 PM PST 24	18642411 ps
T35	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.480386911	Jan 03 12:24:34 PM PST 24	Jan 03 12:24:38 PM PST 24	59882732 ps
T11	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1942352272	Jan 03 12:45:02 PM PST 24	Jan 03 12:46:47 PM PST 24	132224891 ps
T29	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2618069305	Jan 03 12:29:45 PM PST 24	Jan 03 12:30:26 PM PST 24	61655523 ps
T12	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3358677411	Jan 03 12:30:10 PM PST 24	Jan 03 12:30:58 PM PST 24	38881987 ps
T13	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.892490638	Jan 03 12:29:48 PM PST 24	Jan 03 12:30:30 PM PST 24	99412837 ps
T30	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1641620124	Jan 03 12:22:58 PM PST 24	Jan 03 12:23:00 PM PST 24	66755897 ps
T14	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1476767128	Jan 03 12:30:07 PM PST 24	Jan 03 12:30:54 PM PST 24	31018348 ps
T15	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2862003088	Jan 03 12:26:06 PM PST 24	Jan 03 12:26:08 PM PST 24	63429866 ps
T23	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3614729584	Jan 03 12:30:22 PM PST 24	Jan 03 12:31:18 PM PST 24	64051776 ps
T32	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.4156645822	Jan 03 12:28:57 PM PST 24	Jan 03 12:29:24 PM PST 24	29841428 ps
T16	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.250918635	Jan 03 12:39:38 PM PST 24	Jan 03 12:41:04 PM PST 24	45938465 ps
T21	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3991610898	Jan 03 12:33:48 PM PST 24	Jan 03 12:35:22 PM PST 24	156195957 ps
T17	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.769115136	Jan 03 12:25:22 PM PST 24	Jan 03 12:25:25 PM PST 24	59679147 ps
T22	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.2072415439	Jan 03 12:30:07 PM PST 24	Jan 03 12:30:54 PM PST 24	38611675 ps
T18	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2766799919	Jan 03 12:29:27 PM PST 24	Jan 03 12:30:00 PM PST 24	43924009 ps
T19	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1167945138	Jan 03 12:28:42 PM PST 24	Jan 03 12:29:05 PM PST 24	47033058 ps
T41	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2755353377	Jan 03 12:24:13 PM PST 24	Jan 03 12:24:17 PM PST 24	40391622 ps
T33	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.2077744621	Jan 03 12:28:21 PM PST 24	Jan 03 12:28:31 PM PST 24	29690157 ps
T34	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.2457587777	Jan 03 12:30:55 PM PST 24	Jan 03 12:32:01 PM PST 24	28059558 ps
T70	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3301432942	Jan 03 12:30:37 PM PST 24	Jan 03 12:31:46 PM PST 24	369966145 ps
T45	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.873044692	Jan 03 12:27:36 PM PST 24	Jan 03 12:27:43 PM PST 24	123047566 ps
T27	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3046498067	Jan 03 12:44:33 PM PST 24	Jan 03 12:46:03 PM PST 24	66278238 ps
T46	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1208507170	Jan 03 12:29:49 PM PST 24	Jan 03 12:30:34 PM PST 24	311786593 ps
T47	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.384616639	Jan 03 12:27:26 PM PST 24	Jan 03 12:27:33 PM PST 24	20674192 ps
T44	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3166776437	Jan 03 12:23:07 PM PST 24	Jan 03 12:23:11 PM PST 24	297976734 ps
T42	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1545263035	Jan 03 12:41:44 PM PST 24	Jan 03 12:43:18 PM PST 24	194929338 ps
T51	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.299746217	Jan 03 12:42:14 PM PST 24	Jan 03 12:43:38 PM PST 24	60392847 ps
T90	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2733955132	Jan 03 12:30:17 PM PST 24	Jan 03 12:31:08 PM PST 24	43120102 ps
T48	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1261475009	Jan 03 12:39:41 PM PST 24	Jan 03 12:41:20 PM PST 24	30516092 ps
T78	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.2363197626	Jan 03 12:27:17 PM PST 24	Jan 03 12:27:20 PM PST 24	30804281 ps
T20	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2961313313	Jan 03 12:29:52 PM PST 24	Jan 03 12:30:36 PM PST 24	85817558 ps
T71	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3532460774	Jan 03 12:31:00 PM PST 24	Jan 03 12:32:08 PM PST 24	26262309 ps
T63	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3402064799	Jan 03 12:29:27 PM PST 24	Jan 03 12:30:03 PM PST 24	383349087 ps
T89	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3198328657	Jan 03 12:27:30 PM PST 24	Jan 03 12:27:37 PM PST 24	56665190 ps
T64	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2943711668	Jan 03 12:22:42 PM PST 24	Jan 03 12:22:44 PM PST 24	132040766 ps
T36	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3463886430	Jan 03 12:29:49 PM PST 24	Jan 03 12:30:33 PM PST 24	176578803 ps
T91	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3220024373	Jan 03 12:24:08 PM PST 24	Jan 03 12:24:14 PM PST 24	80721072 ps
T37	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3403639939	Jan 03 12:29:44 PM PST 24	Jan 03 12:30:26 PM PST 24	55018610 ps
T81	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.2450715049	Jan 03 12:30:10 PM PST 24	Jan 03 12:30:58 PM PST 24	52103692 ps
T84	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2137929589	Jan 03 12:30:44 PM PST 24	Jan 03 12:31:50 PM PST 24	30322454 ps
T80	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2045443124	Jan 03 12:27:19 PM PST 24	Jan 03 12:27:24 PM PST 24	27409541 ps
T49	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.430068136	Jan 03 12:44:44 PM PST 24	Jan 03 12:46:15 PM PST 24	62252333 ps
T38	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1541009686	Jan 03 12:23:18 PM PST 24	Jan 03 12:23:20 PM PST 24	40753572 ps
T53	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2069438511	Jan 03 12:30:19 PM PST 24	Jan 03 12:31:13 PM PST 24	173856988 ps
T54	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3977260195	Jan 03 12:29:17 PM PST 24	Jan 03 12:29:47 PM PST 24	118371818 ps
T55	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3069428563	Jan 03 12:22:58 PM PST 24	Jan 03 12:23:00 PM PST 24	50170649 ps
T56	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3517186855	Jan 03 12:29:19 PM PST 24	Jan 03 12:29:50 PM PST 24	156019700 ps
T50	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2808683823	Jan 03 12:30:07 PM PST 24	Jan 03 12:30:54 PM PST 24	24539656 ps
T85	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.314413236	Jan 03 12:23:35 PM PST 24	Jan 03 12:23:36 PM PST 24	27683225 ps
T39	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3552453359	Jan 03 12:39:53 PM PST 24	Jan 03 12:41:43 PM PST 24	139373787 ps
T43	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.9284447	Jan 03 12:31:07 PM PST 24	Jan 03 12:32:15 PM PST 24	336772803 ps
T72	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.1596344460	Jan 03 12:24:51 PM PST 24	Jan 03 12:24:53 PM PST 24	23190095 ps
T92	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1544143066	Jan 03 12:29:44 PM PST 24	Jan 03 12:30:26 PM PST 24	335703859 ps
T93	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3494680961	Jan 03 12:30:37 PM PST 24	Jan 03 12:31:39 PM PST 24	35047097 ps
T94	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2678092990	Jan 03 12:25:16 PM PST 24	Jan 03 12:25:20 PM PST 24	143527773 ps
T40	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2470878713	Jan 03 12:28:15 PM PST 24	Jan 03 12:28:24 PM PST 24	183640154 ps
T26	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1108535915	Jan 03 12:27:37 PM PST 24	Jan 03 12:27:41 PM PST 24	23294284 ps
T95	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4126451340	Jan 03 12:35:47 PM PST 24	Jan 03 12:37:31 PM PST 24	50681355 ps
T65	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.602505978	Jan 03 12:29:33 PM PST 24	Jan 03 12:30:09 PM PST 24	88290349 ps
T82	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.368875165	Jan 03 12:27:48 PM PST 24	Jan 03 12:27:51 PM PST 24	27404050 ps
T52	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3581405909	Jan 03 12:29:18 PM PST 24	Jan 03 12:29:48 PM PST 24	35326254 ps
T83	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2700593311	Jan 03 12:30:07 PM PST 24	Jan 03 12:30:54 PM PST 24	22962176 ps
T62	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2970240195	Jan 03 12:44:14 PM PST 24	Jan 03 12:45:28 PM PST 24	136010889 ps
T96	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4201363384	Jan 03 12:25:10 PM PST 24	Jan 03 12:25:16 PM PST 24	78535264 ps
T97	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4281971439	Jan 03 12:29:17 PM PST 24	Jan 03 12:29:46 PM PST 24	32145669 ps
T98	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.565949440	Jan 03 12:23:47 PM PST 24	Jan 03 12:23:50 PM PST 24	126007542 ps
T99	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.539805942	Jan 03 12:22:42 PM PST 24	Jan 03 12:22:46 PM PST 24	57214563 ps
T100	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1991962245	Jan 03 12:29:28 PM PST 24	Jan 03 12:30:01 PM PST 24	25796618 ps
T61	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2689953763	Jan 03 12:29:49 PM PST 24	Jan 03 12:30:32 PM PST 24	44738954 ps
T79	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1029834021	Jan 03 12:29:34 PM PST 24	Jan 03 12:30:10 PM PST 24	22525301 ps
T101	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2982064376	Jan 03 12:30:22 PM PST 24	Jan 03 12:31:17 PM PST 24	34304199 ps
T102	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2032527163	Jan 03 12:31:00 PM PST 24	Jan 03 12:32:08 PM PST 24	23608713 ps
T103	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3659333500	Jan 03 12:26:14 PM PST 24	Jan 03 12:26:16 PM PST 24	161061918 ps
T104	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.2884352276	Jan 03 12:30:51 PM PST 24	Jan 03 12:31:58 PM PST 24	28928501 ps
T28	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1324293043	Jan 03 12:27:25 PM PST 24	Jan 03 12:27:32 PM PST 24	61344333 ps
T105	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1514103651	Jan 03 12:24:51 PM PST 24	Jan 03 12:24:53 PM PST 24	32380416 ps
T66	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3941108950	Jan 03 12:27:48 PM PST 24	Jan 03 12:27:51 PM PST 24	42523332 ps
T106	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2401783860	Jan 03 12:35:47 PM PST 24	Jan 03 12:37:34 PM PST 24	201407158 ps
T107	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1815411682	Jan 03 12:30:26 PM PST 24	Jan 03 12:31:25 PM PST 24	74932992 ps
T77	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1900429034	Jan 03 12:22:42 PM PST 24	Jan 03 12:22:46 PM PST 24	212145591 ps
T57	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4028744974	Jan 03 12:29:31 PM PST 24	Jan 03 12:30:06 PM PST 24	97788739 ps
T108	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2662247201	Jan 03 12:26:09 PM PST 24	Jan 03 12:26:11 PM PST 24	43546760 ps
T109	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3920797232	Jan 03 12:30:52 PM PST 24	Jan 03 12:31:58 PM PST 24	27748671 ps
T110	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2673346113	Jan 03 12:28:29 PM PST 24	Jan 03 12:28:42 PM PST 24	23469553 ps
T88	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.486752584	Jan 03 12:30:29 PM PST 24	Jan 03 12:31:29 PM PST 24	26848413 ps
T111	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2890787898	Jan 03 12:30:18 PM PST 24	Jan 03 12:31:13 PM PST 24	308947050 ps
T112	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3389955497	Jan 03 12:30:06 PM PST 24	Jan 03 12:30:54 PM PST 24	142036648 ps
T76	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2119550486	Jan 03 12:29:50 PM PST 24	Jan 03 12:30:34 PM PST 24	259390982 ps
T113	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2677124671	Jan 03 12:23:42 PM PST 24	Jan 03 12:23:44 PM PST 24	21155680 ps
T114	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3354967845	Jan 03 12:41:48 PM PST 24	Jan 03 12:43:16 PM PST 24	241853765 ps
T115	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3403002654	Jan 03 12:26:07 PM PST 24	Jan 03 12:26:09 PM PST 24	117202366 ps
T116	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4284397056	Jan 03 12:27:36 PM PST 24	Jan 03 12:27:49 PM PST 24	377299845 ps
T67	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1727142146	Jan 03 12:44:05 PM PST 24	Jan 03 12:45:37 PM PST 24	127515199 ps
T117	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1009524160	Jan 03 12:42:36 PM PST 24	Jan 03 12:44:02 PM PST 24	327783738 ps
T86	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1135238424	Jan 03 12:30:46 PM PST 24	Jan 03 12:31:52 PM PST 24	126917046 ps
T74	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2774410356	Jan 03 12:30:21 PM PST 24	Jan 03 12:31:18 PM PST 24	295712343 ps
T118	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4050872	Jan 03 12:27:49 PM PST 24	Jan 03 12:27:53 PM PST 24	122305596 ps
T119	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.893012501	Jan 03 12:27:49 PM PST 24	Jan 03 12:27:54 PM PST 24	311798536 ps
T120	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1821412618	Jan 03 12:39:40 PM PST 24	Jan 03 12:41:05 PM PST 24	26316110 ps
T68	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4121989680	Jan 03 12:30:33 PM PST 24	Jan 03 12:31:36 PM PST 24	150384571 ps
T58	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4245312082	Jan 03 12:29:30 PM PST 24	Jan 03 12:30:07 PM PST 24	208149113 ps
T87	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.1370967571	Jan 03 12:27:24 PM PST 24	Jan 03 12:27:30 PM PST 24	26377938 ps
T121	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3121365826	Jan 03 12:30:07 PM PST 24	Jan 03 12:30:55 PM PST 24	59663674 ps
T122	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.673446117	Jan 03 12:29:30 PM PST 24	Jan 03 12:30:05 PM PST 24	190537215 ps
T75	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1102829391	Jan 03 12:30:23 PM PST 24	Jan 03 12:31:22 PM PST 24	241447359 ps
T59	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2859475145	Jan 03 12:28:42 PM PST 24	Jan 03 12:29:05 PM PST 24	41763703 ps
T123	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2099265591	Jan 03 12:27:25 PM PST 24	Jan 03 12:27:33 PM PST 24	262236475 ps
T124	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1771074619	Jan 03 12:29:38 PM PST 24	Jan 03 12:30:16 PM PST 24	23358860 ps
T125	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3576126555	Jan 03 12:38:57 PM PST 24	Jan 03 12:40:21 PM PST 24	32475485 ps
T126	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.575782724	Jan 03 12:23:51 PM PST 24	Jan 03 12:23:55 PM PST 24	326251481 ps
T127	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.46308610	Jan 03 12:35:33 PM PST 24	Jan 03 12:37:06 PM PST 24	30852819 ps
T128	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.843157489	Jan 03 12:28:42 PM PST 24	Jan 03 12:29:05 PM PST 24	28829412 ps
T129	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.634672506	Jan 03 12:26:14 PM PST 24	Jan 03 12:26:16 PM PST 24	46559440 ps
T69	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.565010056	Jan 03 12:30:36 PM PST 24	Jan 03 12:31:39 PM PST 24	29418885 ps
T130	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1640701381	Jan 03 12:26:29 PM PST 24	Jan 03 12:26:30 PM PST 24	45208555 ps
T131	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.125155042	Jan 03 12:30:24 PM PST 24	Jan 03 12:31:19 PM PST 24	26536105 ps
T132	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1184741603	Jan 03 12:30:37 PM PST 24	Jan 03 12:31:40 PM PST 24	58039970 ps
T133	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1250915282	Jan 03 12:27:31 PM PST 24	Jan 03 12:27:38 PM PST 24	59798162 ps
T134	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.2170558958	Jan 03 12:23:55 PM PST 24	Jan 03 12:23:56 PM PST 24	24243257 ps
T135	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1153490001	Jan 03 12:27:39 PM PST 24	Jan 03 12:27:45 PM PST 24	27982339 ps
T136	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.2337112960	Jan 03 12:30:39 PM PST 24	Jan 03 12:31:43 PM PST 24	40266806 ps
T60	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.915992803	Jan 03 12:30:39 PM PST 24	Jan 03 12:31:44 PM PST 24	71152899 ps
T137	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3368352750	Jan 03 12:29:44 PM PST 24	Jan 03 12:30:25 PM PST 24	65587161 ps
T138	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.443844345	Jan 03 12:30:23 PM PST 24	Jan 03 12:31:19 PM PST 24	40402035 ps
T139	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3741969514	Jan 03 12:39:44 PM PST 24	Jan 03 12:41:56 PM PST 24	22056004 ps
T140	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.766525314	Jan 03 12:23:56 PM PST 24	Jan 03 12:23:59 PM PST 24	86215909 ps
T141	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2096441321	Jan 03 12:23:07 PM PST 24	Jan 03 12:23:10 PM PST 24	88346745 ps
T142	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2202648171	Jan 03 12:38:56 PM PST 24	Jan 03 12:40:03 PM PST 24	66626189 ps
T143	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2851085260	Jan 03 12:30:22 PM PST 24	Jan 03 12:31:17 PM PST 24	33496895 ps
T144	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1453424908	Jan 03 12:26:14 PM PST 24	Jan 03 12:26:16 PM PST 24	124001049 ps
T73	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1690430242	Jan 03 12:33:55 PM PST 24	Jan 03 12:35:20 PM PST 24	333059438 ps
T145	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3421611803	Jan 03 12:32:48 PM PST 24	Jan 03 12:34:51 PM PST 24	272652416 ps
T24	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.214799093	Jan 03 12:23:36 PM PST 24	Jan 03 12:23:38 PM PST 24	56955614 ps
T146	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.158363252	Jan 03 12:24:49 PM PST 24	Jan 03 12:24:53 PM PST 24	280158567 ps
T147	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.2840457919	Jan 03 12:27:16 PM PST 24	Jan 03 12:27:20 PM PST 24	25638547 ps
T148	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.255106720	Jan 03 12:45:03 PM PST 24	Jan 03 12:46:36 PM PST 24	54791945 ps
T25	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.987509980	Jan 03 12:26:14 PM PST 24	Jan 03 12:26:16 PM PST 24	64448584 ps
T149	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3773673366	Jan 03 12:24:42 PM PST 24	Jan 03 12:24:44 PM PST 24	60613333 ps
T150	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.4006174492	Jan 03 12:24:14 PM PST 24	Jan 03 12:24:18 PM PST 24	45302585 ps
T151	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3050938976	Jan 03 12:28:29 PM PST 24	Jan 03 12:28:42 PM PST 24	22727142 ps
T152	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1571952348	Jan 03 12:22:42 PM PST 24	Jan 03 12:22:45 PM PST 24	44966683 ps

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2398169677
Short name	T8
Test name
Test status
Simulation time	255935049 ps
CPU time	4.2 seconds
Started	Jan 03 12:25:22 PM PST 24
Finished	Jan 03 12:25:29 PM PST 24
Peak memory	201660 kb
Host	smart-e112f2fc-b600-48b7-86c4-ab8120582bde
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2398169677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2398169677
Directory	/workspace/16.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/4.usbdev_sec_cm.4179985437
Short name	T3
Test name
Test status
Simulation time	156754151 ps
CPU time	1.03 seconds
Started	Jan 03 12:27:59 PM PST 24
Finished	Jan 03 12:28:10 PM PST 24
Peak memory	220892 kb
Host	smart-abfbbc51-c75a-445b-9fff-9b3fdbaaaf99
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4179985437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.4179985437
Directory	/workspace/4.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.2457587777
Short name	T34
Test name
Test status
Simulation time	28059558 ps
CPU time	0.62 seconds
Started	Jan 03 12:30:55 PM PST 24
Finished	Jan 03 12:32:01 PM PST 24
Peak memory	200356 kb
Host	smart-e61892be-2896-4818-a3a2-8e257ae77b0d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2457587777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2457587777
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2045443124
Short name	T80
Test name
Test status
Simulation time	27409541 ps
CPU time	0.68 seconds
Started	Jan 03 12:27:19 PM PST 24
Finished	Jan 03 12:27:24 PM PST 24
Peak memory	198684 kb
Host	smart-7a126e2c-321f-4be9-acd7-16d14ae3d7da
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2045443124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2045443124
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1942352272
Short name	T11
Test name
Test status
Simulation time	132224891 ps
CPU time	1.77 seconds
Started	Jan 03 12:45:02 PM PST 24
Finished	Jan 03 12:46:47 PM PST 24
Peak memory	201660 kb
Host	smart-e374741a-1776-4509-a20b-7947287e1c10
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1942352272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1942352272
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3166776437
Short name	T44
Test name
Test status
Simulation time	297976734 ps
CPU time	2.69 seconds
Started	Jan 03 12:23:07 PM PST 24
Finished	Jan 03 12:23:11 PM PST 24
Peak memory	201492 kb
Host	smart-f796ca73-e2dc-47e6-b5ee-dbd62e597621
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3166776437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3166776437
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.214799093
Short name	T24
Test name
Test status
Simulation time	56955614 ps
CPU time	0.75 seconds
Started	Jan 03 12:23:36 PM PST 24
Finished	Jan 03 12:23:38 PM PST 24
Peak memory	201488 kb
Host	smart-e8f6dd4f-d8fe-46e5-923b-2cb7acdd394c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214799093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.214799093
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.2072415439
Short name	T22
Test name
Test status
Simulation time	38611675 ps
CPU time	0.6 seconds
Started	Jan 03 12:30:07 PM PST 24
Finished	Jan 03 12:30:54 PM PST 24
Peak memory	200400 kb
Host	smart-0cbb8045-f446-47d3-9fe9-598044f05870
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2072415439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2072415439
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2862003088
Short name	T15
Test name
Test status
Simulation time	63429866 ps
CPU time	2.07 seconds
Started	Jan 03 12:26:06 PM PST 24
Finished	Jan 03 12:26:08 PM PST 24
Peak memory	201768 kb
Host	smart-c80dfbd4-0b16-4de7-a20d-22b841e88c82
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2862003088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2862003088
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1135238424
Short name	T86
Test name
Test status
Simulation time	126917046 ps
CPU time	0.72 seconds
Started	Jan 03 12:30:46 PM PST 24
Finished	Jan 03 12:31:52 PM PST 24
Peak memory	200348 kb
Host	smart-18f24949-282d-4023-884d-75c8cca13845
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1135238424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1135238424
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2119550486
Short name	T76
Test name
Test status
Simulation time	259390982 ps
CPU time	2.51 seconds
Started	Jan 03 12:29:50 PM PST 24
Finished	Jan 03 12:30:34 PM PST 24
Peak memory	201312 kb
Host	smart-61594dd5-7ee2-4277-8caf-64c0ac25b079
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2119550486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2119550486
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1029834021
Short name	T79
Test name
Test status
Simulation time	22525301 ps
CPU time	0.62 seconds
Started	Jan 03 12:29:34 PM PST 24
Finished	Jan 03 12:30:10 PM PST 24
Peak memory	200384 kb
Host	smart-9a273e60-a418-484f-9c76-6f4c48d5a4c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1029834021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1029834021
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3552453359
Short name	T39
Test name
Test status
Simulation time	139373787 ps
CPU time	2.49 seconds
Started	Jan 03 12:39:53 PM PST 24
Finished	Jan 03 12:41:43 PM PST 24
Peak memory	201664 kb
Host	smart-ef0aa57d-8247-4455-9c45-e57a5da3b735
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3552453359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3552453359
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.575782724
Short name	T126
Test name
Test status
Simulation time	326251481 ps
CPU time	3.26 seconds
Started	Jan 03 12:23:51 PM PST 24
Finished	Jan 03 12:23:55 PM PST 24
Peak memory	201648 kb
Host	smart-89da89fb-9bb5-4c68-8a61-ef57303b0fa8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=575782724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.575782724
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2766799919
Short name	T18
Test name
Test status
Simulation time	43924009 ps
CPU time	1.42 seconds
Started	Jan 03 12:29:27 PM PST 24
Finished	Jan 03 12:30:00 PM PST 24
Peak memory	209540 kb
Host	smart-adbe2ff4-40be-4469-8673-716b5b7e51f5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766799919 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.2766799919
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1900429034
Short name	T77
Test name
Test status
Simulation time	212145591 ps
CPU time	2.49 seconds
Started	Jan 03 12:22:42 PM PST 24
Finished	Jan 03 12:22:46 PM PST 24
Peak memory	201680 kb
Host	smart-853005b3-92f8-42b5-a4ad-e7564a7dc134
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1900429034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1900429034
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.987509980
Short name	T25
Test name
Test status
Simulation time	64448584 ps
CPU time	0.86 seconds
Started	Jan 03 12:26:14 PM PST 24
Finished	Jan 03 12:26:16 PM PST 24
Peak memory	200508 kb
Host	smart-853b926c-f642-420a-a251-78c056a9dc05
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987509980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.987509980
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.814549922
Short name	T2
Test name
Test status
Simulation time	174273827 ps
CPU time	1.08 seconds
Started	Jan 03 12:25:33 PM PST 24
Finished	Jan 03 12:25:35 PM PST 24
Peak memory	222180 kb
Host	smart-820eb7b9-4f39-4733-be1f-bb398174af72
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=814549922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.814549922
Directory	/workspace/2.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3991610898
Short name	T21
Test name
Test status
Simulation time	156195957 ps
CPU time	1.39 seconds
Started	Jan 03 12:33:48 PM PST 24
Finished	Jan 03 12:35:22 PM PST 24
Peak memory	201280 kb
Host	smart-4a50115c-f163-4def-80cc-fc251dc08ac0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991610898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.3991610898
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1815411682
Short name	T107
Test name
Test status
Simulation time	74932992 ps
CPU time	2.41 seconds
Started	Jan 03 12:30:26 PM PST 24
Finished	Jan 03 12:31:25 PM PST 24
Peak memory	200680 kb
Host	smart-72f0a9da-e19b-4c44-a7a8-b533021d9ae2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1815411682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1815411682
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/1.usbdev_sec_cm.1365330994
Short name	T1
Test name
Test status
Simulation time	167127108 ps
CPU time	1.07 seconds
Started	Jan 03 12:27:59 PM PST 24
Finished	Jan 03 12:28:10 PM PST 24
Peak memory	220824 kb
Host	smart-6c591476-d1ce-42a5-aa5a-9342e8846d9a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1365330994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1365330994
Directory	/workspace/1.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.873044692
Short name	T45
Test name
Test status
Simulation time	123047566 ps
CPU time	3.19 seconds
Started	Jan 03 12:27:36 PM PST 24
Finished	Jan 03 12:27:43 PM PST 24
Peak memory	201464 kb
Host	smart-11400934-c056-478e-bd99-a66cdfcf1fd9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873044692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.873044692
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4284397056
Short name	T116
Test name
Test status
Simulation time	377299845 ps
CPU time	8.63 seconds
Started	Jan 03 12:27:36 PM PST 24
Finished	Jan 03 12:27:49 PM PST 24
Peak memory	201300 kb
Host	smart-85a57ab4-619d-42f4-9d89-86035800852d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284397056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.4284397056
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2662247201
Short name	T108
Test name
Test status
Simulation time	43546760 ps
CPU time	1.02 seconds
Started	Jan 03 12:26:09 PM PST 24
Finished	Jan 03 12:26:11 PM PST 24
Peak memory	201748 kb
Host	smart-cd8ac17e-6565-4ef2-be07-ac5349d6a67c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662247201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2662247201
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.634672506
Short name	T129
Test name
Test status
Simulation time	46559440 ps
CPU time	0.7 seconds
Started	Jan 03 12:26:14 PM PST 24
Finished	Jan 03 12:26:16 PM PST 24
Peak memory	200632 kb
Host	smart-d01c7a6f-ef8c-4f11-a6dd-458e95b3b995
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=634672506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.634672506
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2096441321
Short name	T141
Test name
Test status
Simulation time	88346745 ps
CPU time	2.2 seconds
Started	Jan 03 12:23:07 PM PST 24
Finished	Jan 03 12:23:10 PM PST 24
Peak memory	201460 kb
Host	smart-d6871504-c788-4d96-81a8-d40fbd7b627d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2096441321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2096441321
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.565949440
Short name	T98
Test name
Test status
Simulation time	126007542 ps
CPU time	1.5 seconds
Started	Jan 03 12:23:47 PM PST 24
Finished	Jan 03 12:23:50 PM PST 24
Peak memory	201592 kb
Host	smart-df7f325a-2d40-4d7d-b5d8-0f1d535fae0d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565949440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_cs r_outstanding.565949440
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1541009686
Short name	T38
Test name
Test status
Simulation time	40753572 ps
CPU time	1.28 seconds
Started	Jan 03 12:23:18 PM PST 24
Finished	Jan 03 12:23:20 PM PST 24
Peak memory	201576 kb
Host	smart-7f5d1966-1566-4f0e-8011-ee39af04aac2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1541009686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1541009686
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2890787898
Short name	T111
Test name
Test status
Simulation time	308947050 ps
CPU time	3.32 seconds
Started	Jan 03 12:30:18 PM PST 24
Finished	Jan 03 12:31:13 PM PST 24
Peak memory	201292 kb
Host	smart-9a4b5696-3e75-4e1f-b30c-42ea526f511d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890787898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2890787898
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2401783860
Short name	T106
Test name
Test status
Simulation time	201407158 ps
CPU time	4.59 seconds
Started	Jan 03 12:35:47 PM PST 24
Finished	Jan 03 12:37:34 PM PST 24
Peak memory	201612 kb
Host	smart-87f179f5-f36f-4649-b3b0-034be313ab86
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401783860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2401783860
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1108535915
Short name	T26
Test name
Test status
Simulation time	23294284 ps
CPU time	0.67 seconds
Started	Jan 03 12:27:37 PM PST 24
Finished	Jan 03 12:27:41 PM PST 24
Peak memory	201188 kb
Host	smart-8c175b08-1b75-46ef-815a-3652361041c4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108535915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1108535915
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1476767128
Short name	T14
Test name
Test status
Simulation time	31018348 ps
CPU time	0.96 seconds
Started	Jan 03 12:30:07 PM PST 24
Finished	Jan 03 12:30:54 PM PST 24
Peak memory	207548 kb
Host	smart-9cc0b43e-953c-4d56-8dc9-c2ed962e5f42
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476767128 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.1476767128
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.915992803
Short name	T60
Test name
Test status
Simulation time	71152899 ps
CPU time	1.89 seconds
Started	Jan 03 12:30:39 PM PST 24
Finished	Jan 03 12:31:44 PM PST 24
Peak memory	201272 kb
Host	smart-e279b3a1-856a-434e-8be0-6a78040f72c1
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=915992803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.915992803
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2678092990
Short name	T94
Test name
Test status
Simulation time	143527773 ps
CPU time	2.2 seconds
Started	Jan 03 12:25:16 PM PST 24
Finished	Jan 03 12:25:20 PM PST 24
Peak memory	201520 kb
Host	smart-e54d6bab-e7ff-442d-baf5-1b24cac8c47f
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2678092990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2678092990
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1453424908
Short name	T144
Test name
Test status
Simulation time	124001049 ps
CPU time	1.1 seconds
Started	Jan 03 12:26:14 PM PST 24
Finished	Jan 03 12:26:16 PM PST 24
Peak memory	200604 kb
Host	smart-3980ed9d-1e81-4862-ad1f-54dcd770f73b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453424908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.1453424908
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4126451340
Short name	T95
Test name
Test status
Simulation time	50681355 ps
CPU time	1.08 seconds
Started	Jan 03 12:35:47 PM PST 24
Finished	Jan 03 12:37:31 PM PST 24
Peak memory	201420 kb
Host	smart-d5737e45-8bed-42e6-94a2-0d11a72fa21b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126451340 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.4126451340
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.480386911
Short name	T35
Test name
Test status
Simulation time	59882732 ps
CPU time	0.8 seconds
Started	Jan 03 12:24:34 PM PST 24
Finished	Jan 03 12:24:38 PM PST 24
Peak memory	201368 kb
Host	smart-33ea0bb8-dc66-4cb6-b770-e92a9aff0a06
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480386911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.480386911
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.443844345
Short name	T138
Test name
Test status
Simulation time	40402035 ps
CPU time	0.91 seconds
Started	Jan 03 12:30:23 PM PST 24
Finished	Jan 03 12:31:19 PM PST 24
Peak memory	201128 kb
Host	smart-577fd4b2-e365-4882-8455-196cc5fbdbc8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443844345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_c sr_outstanding.443844345
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3421611803
Short name	T145
Test name
Test status
Simulation time	272652416 ps
CPU time	2.57 seconds
Started	Jan 03 12:32:48 PM PST 24
Finished	Jan 03 12:34:51 PM PST 24
Peak memory	200656 kb
Host	smart-e58ae696-afc6-4aa5-8b98-7205c9012db9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3421611803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3421611803
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3121365826
Short name	T121
Test name
Test status
Simulation time	59663674 ps
CPU time	1.43 seconds
Started	Jan 03 12:30:07 PM PST 24
Finished	Jan 03 12:30:55 PM PST 24
Peak memory	199440 kb
Host	smart-fed5c9ff-b01e-48aa-8148-e6b58c62c7c7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121365826 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.3121365826
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.881777902
Short name	T6
Test name
Test status
Simulation time	64475921 ps
CPU time	0.78 seconds
Started	Jan 03 12:29:30 PM PST 24
Finished	Jan 03 12:30:04 PM PST 24
Peak memory	200980 kb
Host	smart-953e9364-33c7-4f1b-9615-17b34c133244
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881777902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.881777902
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.46308610
Short name	T127
Test name
Test status
Simulation time	30852819 ps
CPU time	0.62 seconds
Started	Jan 03 12:35:33 PM PST 24
Finished	Jan 03 12:37:06 PM PST 24
Peak memory	200884 kb
Host	smart-b764d2c6-4759-4403-a323-753e4e5c0a23
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=46308610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.46308610
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3977260195
Short name	T54
Test name
Test status
Simulation time	118371818 ps
CPU time	1.39 seconds
Started	Jan 03 12:29:17 PM PST 24
Finished	Jan 03 12:29:47 PM PST 24
Peak memory	201096 kb
Host	smart-f5556815-3ac1-4cd8-ad9a-4bbd4f701561
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977260195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.3977260195
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.673446117
Short name	T122
Test name
Test status
Simulation time	190537215 ps
CPU time	2.02 seconds
Started	Jan 03 12:29:30 PM PST 24
Finished	Jan 03 12:30:05 PM PST 24
Peak memory	201332 kb
Host	smart-dfc1560d-7c43-4644-82aa-63f89c594a97
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=673446117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.673446117
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3069428563
Short name	T55
Test name
Test status
Simulation time	50170649 ps
CPU time	1.38 seconds
Started	Jan 03 12:22:58 PM PST 24
Finished	Jan 03 12:23:00 PM PST 24
Peak memory	209876 kb
Host	smart-05611b8b-354d-4f39-a617-d4b32194a760
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069428563 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.3069428563
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3517186855
Short name	T56
Test name
Test status
Simulation time	156019700 ps
CPU time	1.58 seconds
Started	Jan 03 12:29:19 PM PST 24
Finished	Jan 03 12:29:50 PM PST 24
Peak memory	200648 kb
Host	smart-aaa6ff39-4f66-4fb1-9e49-6aad2d6a36c9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517186855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_ csr_outstanding.3517186855
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1250915282
Short name	T133
Test name
Test status
Simulation time	59798162 ps
CPU time	1.68 seconds
Started	Jan 03 12:27:31 PM PST 24
Finished	Jan 03 12:27:38 PM PST 24
Peak memory	201228 kb
Host	smart-3db115ea-032c-458c-ae7b-4189a8507cdd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1250915282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1250915282
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.843157489
Short name	T128
Test name
Test status
Simulation time	28829412 ps
CPU time	1.26 seconds
Started	Jan 03 12:28:42 PM PST 24
Finished	Jan 03 12:29:05 PM PST 24
Peak memory	201596 kb
Host	smart-afff3c39-a832-4a51-a314-adb143b14500
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843157489 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.843157489
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2808683823
Short name	T50
Test name
Test status
Simulation time	24539656 ps
CPU time	0.84 seconds
Started	Jan 03 12:30:07 PM PST 24
Finished	Jan 03 12:30:54 PM PST 24
Peak memory	200488 kb
Host	smart-763f0757-6e5d-455d-b5c9-752c262f9b8c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808683823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2808683823
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2137929589
Short name	T84
Test name
Test status
Simulation time	30322454 ps
CPU time	0.61 seconds
Started	Jan 03 12:30:44 PM PST 24
Finished	Jan 03 12:31:50 PM PST 24
Peak memory	200344 kb
Host	smart-4e83d18f-0680-44bd-99b2-e826465ae419
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2137929589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2137929589
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2733955132
Short name	T90
Test name
Test status
Simulation time	43120102 ps
CPU time	0.93 seconds
Started	Jan 03 12:30:17 PM PST 24
Finished	Jan 03 12:31:08 PM PST 24
Peak memory	201056 kb
Host	smart-b30a9a6c-b0ff-4256-8abb-3853ae6511cd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733955132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_ csr_outstanding.2733955132
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.4006174492
Short name	T150
Test name
Test status
Simulation time	45302585 ps
CPU time	1.17 seconds
Started	Jan 03 12:24:14 PM PST 24
Finished	Jan 03 12:24:18 PM PST 24
Peak memory	201672 kb
Host	smart-d93ef4d8-8a0c-4f69-8143-3310bdc01fb0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006174492 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.4006174492
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1261475009
Short name	T48
Test name
Test status
Simulation time	30516092 ps
CPU time	0.78 seconds
Started	Jan 03 12:39:41 PM PST 24
Finished	Jan 03 12:41:20 PM PST 24
Peak memory	201524 kb
Host	smart-9c7280d3-466a-434d-ab0a-d607a17acc89
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261475009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1261475009
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3659333500
Short name	T103
Test name
Test status
Simulation time	161061918 ps
CPU time	1.13 seconds
Started	Jan 03 12:26:14 PM PST 24
Finished	Jan 03 12:26:16 PM PST 24
Peak memory	201628 kb
Host	smart-e0aa6839-21d3-4d8e-a243-a99f8bac8d4d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659333500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.3659333500
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2970240195
Short name	T62
Test name
Test status
Simulation time	136010889 ps
CPU time	1.65 seconds
Started	Jan 03 12:44:14 PM PST 24
Finished	Jan 03 12:45:28 PM PST 24
Peak memory	201736 kb
Host	smart-719382f1-7199-4cad-ad8b-863eb20728d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2970240195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2970240195
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3402064799
Short name	T63
Test name
Test status
Simulation time	383349087 ps
CPU time	3.08 seconds
Started	Jan 03 12:29:27 PM PST 24
Finished	Jan 03 12:30:03 PM PST 24
Peak memory	199864 kb
Host	smart-7aece3f4-e157-43a9-a9a9-90ca9978c7bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3402064799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3402064799
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.565010056
Short name	T69
Test name
Test status
Simulation time	29418885 ps
CPU time	0.91 seconds
Started	Jan 03 12:30:36 PM PST 24
Finished	Jan 03 12:31:39 PM PST 24
Peak memory	216824 kb
Host	smart-6e34f61d-01b9-4c84-aacd-5c4d1e86d91b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565010056 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.565010056
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2618069305
Short name	T29
Test name
Test status
Simulation time	61655523 ps
CPU time	0.99 seconds
Started	Jan 03 12:29:45 PM PST 24
Finished	Jan 03 12:30:26 PM PST 24
Peak memory	201284 kb
Host	smart-aef64422-adf9-462b-9d3c-329d3e51ae13
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618069305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2618069305
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.1370967571
Short name	T87
Test name
Test status
Simulation time	26377938 ps
CPU time	0.65 seconds
Started	Jan 03 12:27:24 PM PST 24
Finished	Jan 03 12:27:30 PM PST 24
Peak memory	200024 kb
Host	smart-006daab3-be76-485d-a352-7349a6621632
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1370967571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1370967571
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3463886430
Short name	T36
Test name
Test status
Simulation time	176578803 ps
CPU time	1.96 seconds
Started	Jan 03 12:29:49 PM PST 24
Finished	Jan 03 12:30:33 PM PST 24
Peak memory	201336 kb
Host	smart-a9d6f5b6-ba3d-4ade-b8d8-37647bb00521
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3463886430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3463886430
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1167945138
Short name	T19
Test name
Test status
Simulation time	47033058 ps
CPU time	1.27 seconds
Started	Jan 03 12:28:42 PM PST 24
Finished	Jan 03 12:29:05 PM PST 24
Peak memory	209844 kb
Host	smart-30e2acef-3b7a-4bd6-8aab-b3e221dce497
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167945138 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.1167945138
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2202648171
Short name	T142
Test name
Test status
Simulation time	66626189 ps
CPU time	1.05 seconds
Started	Jan 03 12:38:56 PM PST 24
Finished	Jan 03 12:40:03 PM PST 24
Peak memory	201712 kb
Host	smart-26cd95b3-fb87-44ac-b551-67da7c810650
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202648171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2202648171
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1983708910
Short name	T31
Test name
Test status
Simulation time	18642411 ps
CPU time	0.61 seconds
Started	Jan 03 12:25:05 PM PST 24
Finished	Jan 03 12:25:10 PM PST 24
Peak memory	200776 kb
Host	smart-9789d63c-710d-4542-9ca6-00105eb36563
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1983708910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1983708910
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3614729584
Short name	T23
Test name
Test status
Simulation time	64051776 ps
CPU time	1.38 seconds
Started	Jan 03 12:30:22 PM PST 24
Finished	Jan 03 12:31:18 PM PST 24
Peak memory	201240 kb
Host	smart-724e2130-86f9-4708-b06a-d99434a99d91
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614729584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.3614729584
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3741969514
Short name	T139
Test name
Test status
Simulation time	22056004 ps
CPU time	0.9 seconds
Started	Jan 03 12:39:44 PM PST 24
Finished	Jan 03 12:41:56 PM PST 24
Peak memory	201740 kb
Host	smart-8861e5aa-dd37-487e-a79b-adbc5dc4b61f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741969514 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.3741969514
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.255106720
Short name	T148
Test name
Test status
Simulation time	54791945 ps
CPU time	0.81 seconds
Started	Jan 03 12:45:03 PM PST 24
Finished	Jan 03 12:46:36 PM PST 24
Peak memory	201336 kb
Host	smart-dbb45f06-75f9-496c-9666-2c4dfc300590
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255106720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.255106720
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3333767203
Short name	T10
Test name
Test status
Simulation time	76109133 ps
CPU time	0.97 seconds
Started	Jan 03 12:36:01 PM PST 24
Finished	Jan 03 12:37:41 PM PST 24
Peak memory	201692 kb
Host	smart-0b34b7bd-4675-4541-87f3-bd9a69b13dba
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333767203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.3333767203
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2470878713
Short name	T40
Test name
Test status
Simulation time	183640154 ps
CPU time	1.93 seconds
Started	Jan 03 12:28:15 PM PST 24
Finished	Jan 03 12:28:24 PM PST 24
Peak memory	200716 kb
Host	smart-2418900a-5b28-4bab-9a97-67260bb4ba7b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2470878713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2470878713
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1690430242
Short name	T73
Test name
Test status
Simulation time	333059438 ps
CPU time	2.97 seconds
Started	Jan 03 12:33:55 PM PST 24
Finished	Jan 03 12:35:20 PM PST 24
Peak memory	201368 kb
Host	smart-79c09e5c-59d4-40b2-bf36-1347afc1dfe3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1690430242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1690430242
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1640701381
Short name	T130
Test name
Test status
Simulation time	45208555 ps
CPU time	1.23 seconds
Started	Jan 03 12:26:29 PM PST 24
Finished	Jan 03 12:26:30 PM PST 24
Peak memory	201672 kb
Host	smart-ac6c3621-a2d8-4a69-974e-e87cbca9714a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640701381 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.1640701381
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.368875165
Short name	T82
Test name
Test status
Simulation time	27404050 ps
CPU time	0.65 seconds
Started	Jan 03 12:27:48 PM PST 24
Finished	Jan 03 12:27:51 PM PST 24
Peak memory	200576 kb
Host	smart-578b23e3-6762-4f2a-84a0-e654b061e833
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=368875165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.368875165
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1641620124
Short name	T30
Test name
Test status
Simulation time	66755897 ps
CPU time	1.03 seconds
Started	Jan 03 12:22:58 PM PST 24
Finished	Jan 03 12:23:00 PM PST 24
Peak memory	201592 kb
Host	smart-3fbecc92-5bf9-4f13-840c-b3a752bb93c2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641620124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.1641620124
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3403639939
Short name	T37
Test name
Test status
Simulation time	55018610 ps
CPU time	1.59 seconds
Started	Jan 03 12:29:44 PM PST 24
Finished	Jan 03 12:30:26 PM PST 24
Peak memory	201296 kb
Host	smart-6b24f3a7-eb59-4113-942a-61384af61353
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3403639939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3403639939
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3354967845
Short name	T114
Test name
Test status
Simulation time	241853765 ps
CPU time	4.21 seconds
Started	Jan 03 12:41:48 PM PST 24
Finished	Jan 03 12:43:16 PM PST 24
Peak memory	201692 kb
Host	smart-2b5776a5-55cb-4167-b8b4-75b03d9bca9c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3354967845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3354967845
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1184741603
Short name	T132
Test name
Test status
Simulation time	58039970 ps
CPU time	1.15 seconds
Started	Jan 03 12:30:37 PM PST 24
Finished	Jan 03 12:31:40 PM PST 24
Peak memory	201264 kb
Host	smart-a27cbf29-81bd-4ece-a686-096c47efbb79
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184741603 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.1184741603
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1727142146
Short name	T67
Test name
Test status
Simulation time	127515199 ps
CPU time	0.85 seconds
Started	Jan 03 12:44:05 PM PST 24
Finished	Jan 03 12:45:37 PM PST 24
Peak memory	201348 kb
Host	smart-7d245a22-b62f-4825-a141-3b469db5878b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727142146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1727142146
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.1596344460
Short name	T72
Test name
Test status
Simulation time	23190095 ps
CPU time	0.69 seconds
Started	Jan 03 12:24:51 PM PST 24
Finished	Jan 03 12:24:53 PM PST 24
Peak memory	200676 kb
Host	smart-d0ac9cf5-353c-4de6-a7e1-3d09e29945fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1596344460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1596344460
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3389955497
Short name	T112
Test name
Test status
Simulation time	142036648 ps
CPU time	1.48 seconds
Started	Jan 03 12:30:06 PM PST 24
Finished	Jan 03 12:30:54 PM PST 24
Peak memory	200628 kb
Host	smart-be853db1-fb79-4080-a4f1-634a2d18335f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389955497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.3389955497
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3358677411
Short name	T12
Test name
Test status
Simulation time	38881987 ps
CPU time	1.11 seconds
Started	Jan 03 12:30:10 PM PST 24
Finished	Jan 03 12:30:58 PM PST 24
Peak memory	201232 kb
Host	smart-55f07541-e890-4876-98a3-2a76ddb0e9c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3358677411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3358677411
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.9284447
Short name	T43
Test name
Test status
Simulation time	336772803 ps
CPU time	2.69 seconds
Started	Jan 03 12:31:07 PM PST 24
Finished	Jan 03 12:32:15 PM PST 24
Peak memory	201296 kb
Host	smart-775afd4d-a7df-4002-913b-73aa2801f4b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=9284447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.9284447
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2069438511
Short name	T53
Test name
Test status
Simulation time	173856988 ps
CPU time	1.85 seconds
Started	Jan 03 12:30:19 PM PST 24
Finished	Jan 03 12:31:13 PM PST 24
Peak memory	201064 kb
Host	smart-dc3bb702-2cc8-4179-b196-0af9a665b6c8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069438511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2069438511
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1324293043
Short name	T28
Test name
Test status
Simulation time	61344333 ps
CPU time	0.72 seconds
Started	Jan 03 12:27:25 PM PST 24
Finished	Jan 03 12:27:32 PM PST 24
Peak memory	201004 kb
Host	smart-f784246f-c14b-492f-9d95-840b456d96fe
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324293043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1324293043
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1821412618
Short name	T120
Test name
Test status
Simulation time	26316110 ps
CPU time	0.93 seconds
Started	Jan 03 12:39:40 PM PST 24
Finished	Jan 03 12:41:05 PM PST 24
Peak memory	201656 kb
Host	smart-ec8cf5d7-39b3-4922-ae9d-47b878b7cb45
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821412618 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.1821412618
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3581405909
Short name	T52
Test name
Test status
Simulation time	35326254 ps
CPU time	0.98 seconds
Started	Jan 03 12:29:18 PM PST 24
Finished	Jan 03 12:29:48 PM PST 24
Peak memory	200728 kb
Host	smart-56fb740b-a5cc-4920-87c4-ee0a31ceade0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581405909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3581405909
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.314413236
Short name	T85
Test name
Test status
Simulation time	27683225 ps
CPU time	0.63 seconds
Started	Jan 03 12:23:35 PM PST 24
Finished	Jan 03 12:23:36 PM PST 24
Peak memory	200712 kb
Host	smart-92c0596d-7cf8-469e-b99b-0ac5c36dad20
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=314413236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.314413236
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.892490638
Short name	T13
Test name
Test status
Simulation time	99412837 ps
CPU time	1.29 seconds
Started	Jan 03 12:29:48 PM PST 24
Finished	Jan 03 12:30:30 PM PST 24
Peak memory	201272 kb
Host	smart-33759493-24b8-40c6-ad8c-d2e6b51536d9
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=892490638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.892490638
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1544143066
Short name	T92
Test name
Test status
Simulation time	335703859 ps
CPU time	1.62 seconds
Started	Jan 03 12:29:44 PM PST 24
Finished	Jan 03 12:30:26 PM PST 24
Peak memory	201216 kb
Host	smart-88effa1f-3b7a-4d84-9b16-126082f80843
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544143066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c sr_outstanding.1544143066
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2961313313
Short name	T20
Test name
Test status
Simulation time	85817558 ps
CPU time	1.26 seconds
Started	Jan 03 12:29:52 PM PST 24
Finished	Jan 03 12:30:36 PM PST 24
Peak memory	201308 kb
Host	smart-939ed1b6-7a97-4836-92af-843710edefc3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2961313313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2961313313
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.125155042
Short name	T131
Test name
Test status
Simulation time	26536105 ps
CPU time	0.61 seconds
Started	Jan 03 12:30:24 PM PST 24
Finished	Jan 03 12:31:19 PM PST 24
Peak memory	200436 kb
Host	smart-a020a386-a6f1-4ad7-9660-83b47d3f0665
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=125155042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.125155042
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.2077744621
Short name	T33
Test name
Test status
Simulation time	29690157 ps
CPU time	0.62 seconds
Started	Jan 03 12:28:21 PM PST 24
Finished	Jan 03 12:28:31 PM PST 24
Peak memory	200572 kb
Host	smart-b7bc4788-5531-4a2b-b1cd-e8d71266d63b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2077744621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2077744621
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2982064376
Short name	T101
Test name
Test status
Simulation time	34304199 ps
CPU time	0.64 seconds
Started	Jan 03 12:30:22 PM PST 24
Finished	Jan 03 12:31:17 PM PST 24
Peak memory	200316 kb
Host	smart-953e8009-877a-4907-b73e-d4b9c303f9a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2982064376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2982064376
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.2363197626
Short name	T78
Test name
Test status
Simulation time	30804281 ps
CPU time	0.62 seconds
Started	Jan 03 12:27:17 PM PST 24
Finished	Jan 03 12:27:20 PM PST 24
Peak memory	200272 kb
Host	smart-08659bac-788c-412d-aa30-68da5aa442a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2363197626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2363197626
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.2337112960
Short name	T136
Test name
Test status
Simulation time	40266806 ps
CPU time	0.63 seconds
Started	Jan 03 12:30:39 PM PST 24
Finished	Jan 03 12:31:43 PM PST 24
Peak memory	200292 kb
Host	smart-40fee07e-64a3-4407-ba5d-62257cf39e44
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2337112960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2337112960
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1514103651
Short name	T105
Test name
Test status
Simulation time	32380416 ps
CPU time	0.67 seconds
Started	Jan 03 12:24:51 PM PST 24
Finished	Jan 03 12:24:53 PM PST 24
Peak memory	200684 kb
Host	smart-0930ad5e-a22e-43e2-8fb5-f005e7cb7184
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1514103651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1514103651
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.2450715049
Short name	T81
Test name
Test status
Simulation time	52103692 ps
CPU time	0.68 seconds
Started	Jan 03 12:30:10 PM PST 24
Finished	Jan 03 12:30:58 PM PST 24
Peak memory	199528 kb
Host	smart-bc10e023-cb78-404c-9bce-a56f1922400b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2450715049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2450715049
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4239734569
Short name	T7
Test name
Test status
Simulation time	327463055 ps
CPU time	3.4 seconds
Started	Jan 03 12:30:49 PM PST 24
Finished	Jan 03 12:31:58 PM PST 24
Peak memory	201328 kb
Host	smart-c02d6f73-16e6-49cf-854f-5ddba721b5f5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239734569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.4239734569
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3301432942
Short name	T70
Test name
Test status
Simulation time	369966145 ps
CPU time	7.91 seconds
Started	Jan 03 12:30:37 PM PST 24
Finished	Jan 03 12:31:46 PM PST 24
Peak memory	200536 kb
Host	smart-9ef1557c-35f8-45ac-8ee5-4b83d42a4c56
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301432942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3301432942
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.250918635
Short name	T16
Test name
Test status
Simulation time	45938465 ps
CPU time	1.99 seconds
Started	Jan 03 12:39:38 PM PST 24
Finished	Jan 03 12:41:04 PM PST 24
Peak memory	209988 kb
Host	smart-0b9b353a-9148-4de2-9433-64d2eeb64e69
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250918635 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.250918635
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3494680961
Short name	T93
Test name
Test status
Simulation time	35047097 ps
CPU time	0.76 seconds
Started	Jan 03 12:30:37 PM PST 24
Finished	Jan 03 12:31:39 PM PST 24
Peak memory	200964 kb
Host	smart-d9a2dd9b-8324-48c2-85fe-3f777881086b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494680961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3494680961
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3576126555
Short name	T125
Test name
Test status
Simulation time	32475485 ps
CPU time	0.64 seconds
Started	Jan 03 12:38:57 PM PST 24
Finished	Jan 03 12:40:21 PM PST 24
Peak memory	200756 kb
Host	smart-6e44f6ff-ae81-4322-b79f-1aa2a1d86904
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3576126555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3576126555
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.430068136
Short name	T49
Test name
Test status
Simulation time	62252333 ps
CPU time	1.96 seconds
Started	Jan 03 12:44:44 PM PST 24
Finished	Jan 03 12:46:15 PM PST 24
Peak memory	201492 kb
Host	smart-c44fbfe7-68ea-4211-b792-ef7707cc3c7c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=430068136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.430068136
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.766525314
Short name	T140
Test name
Test status
Simulation time	86215909 ps
CPU time	2.26 seconds
Started	Jan 03 12:23:56 PM PST 24
Finished	Jan 03 12:23:59 PM PST 24
Peak memory	201572 kb
Host	smart-0255469f-6b0e-4f29-a502-56e16cdd335a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=766525314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.766525314
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4121989680
Short name	T68
Test name
Test status
Simulation time	150384571 ps
CPU time	1.45 seconds
Started	Jan 03 12:30:33 PM PST 24
Finished	Jan 03 12:31:36 PM PST 24
Peak memory	201264 kb
Host	smart-9fb1436d-5f87-4fca-ba04-c897f5891801
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121989680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.4121989680
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2689953763
Short name	T61
Test name
Test status
Simulation time	44738954 ps
CPU time	1.07 seconds
Started	Jan 03 12:29:49 PM PST 24
Finished	Jan 03 12:30:32 PM PST 24
Peak memory	201392 kb
Host	smart-7142c1bd-7084-4be6-b8c3-945df459834d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2689953763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2689953763
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.2884352276
Short name	T104
Test name
Test status
Simulation time	28928501 ps
CPU time	0.62 seconds
Started	Jan 03 12:30:51 PM PST 24
Finished	Jan 03 12:31:58 PM PST 24
Peak memory	200420 kb
Host	smart-9e38165f-d489-4c3b-9ce9-a1b214d5c03e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2884352276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2884352276
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3532460774
Short name	T71
Test name
Test status
Simulation time	26262309 ps
CPU time	0.62 seconds
Started	Jan 03 12:31:00 PM PST 24
Finished	Jan 03 12:32:08 PM PST 24
Peak memory	200596 kb
Host	smart-3297f9d3-3552-41bd-9de9-2da7d0d41868
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3532460774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3532460774
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3920797232
Short name	T109
Test name
Test status
Simulation time	27748671 ps
CPU time	0.6 seconds
Started	Jan 03 12:30:52 PM PST 24
Finished	Jan 03 12:31:58 PM PST 24
Peak memory	200348 kb
Host	smart-adf1ca83-7682-48ea-82dd-fc32e0e61cab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3920797232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3920797232
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2032527163
Short name	T102
Test name
Test status
Simulation time	23608713 ps
CPU time	0.63 seconds
Started	Jan 03 12:31:00 PM PST 24
Finished	Jan 03 12:32:08 PM PST 24
Peak memory	200400 kb
Host	smart-72b3e697-3cf3-47ba-9292-211ac16112c3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2032527163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2032527163
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.2840457919
Short name	T147
Test name
Test status
Simulation time	25638547 ps
CPU time	0.65 seconds
Started	Jan 03 12:27:16 PM PST 24
Finished	Jan 03 12:27:20 PM PST 24
Peak memory	199560 kb
Host	smart-b4970cd8-ad1a-4f23-8401-e8384ac0b121
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2840457919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2840457919
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.486752584
Short name	T88
Test name
Test status
Simulation time	26848413 ps
CPU time	0.61 seconds
Started	Jan 03 12:30:29 PM PST 24
Finished	Jan 03 12:31:29 PM PST 24
Peak memory	200364 kb
Host	smart-a5d4d0ea-01e5-47b8-92b4-284a822524fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=486752584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.486752584
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1153490001
Short name	T135
Test name
Test status
Simulation time	27982339 ps
CPU time	0.63 seconds
Started	Jan 03 12:27:39 PM PST 24
Finished	Jan 03 12:27:45 PM PST 24
Peak memory	200624 kb
Host	smart-8642e625-af10-4549-b447-56b5feb6a8b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1153490001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1153490001
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1208507170
Short name	T46
Test name
Test status
Simulation time	311786593 ps
CPU time	3.4 seconds
Started	Jan 03 12:29:49 PM PST 24
Finished	Jan 03 12:30:34 PM PST 24
Peak memory	201360 kb
Host	smart-677c46f5-7ac5-4636-aca7-5213799352ca
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208507170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1208507170
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4245312082
Short name	T58
Test name
Test status
Simulation time	208149113 ps
CPU time	4.4 seconds
Started	Jan 03 12:29:30 PM PST 24
Finished	Jan 03 12:30:07 PM PST 24
Peak memory	201300 kb
Host	smart-8e7a9205-6b58-4d5f-9147-8c17ff7a973c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245312082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.4245312082
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3046498067
Short name	T27
Test name
Test status
Simulation time	66278238 ps
CPU time	0.81 seconds
Started	Jan 03 12:44:33 PM PST 24
Finished	Jan 03 12:46:03 PM PST 24
Peak memory	201452 kb
Host	smart-71008c6b-e074-4a70-bbf5-74ef3823232b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046498067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3046498067
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.539805942
Short name	T99
Test name
Test status
Simulation time	57214563 ps
CPU time	1.73 seconds
Started	Jan 03 12:22:42 PM PST 24
Finished	Jan 03 12:22:46 PM PST 24
Peak memory	209904 kb
Host	smart-f1c5b1b8-0365-4cee-a8bf-27c1e27d44af
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539805942 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.539805942
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4201363384
Short name	T96
Test name
Test status
Simulation time	78535264 ps
CPU time	1.17 seconds
Started	Jan 03 12:25:10 PM PST 24
Finished	Jan 03 12:25:16 PM PST 24
Peak memory	200668 kb
Host	smart-40834ca8-a998-45dd-be12-cd82869d6086
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201363384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.4201363384
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4028744974
Short name	T57
Test name
Test status
Simulation time	97788739 ps
CPU time	1.29 seconds
Started	Jan 03 12:29:31 PM PST 24
Finished	Jan 03 12:30:06 PM PST 24
Peak memory	201120 kb
Host	smart-31bbf1ad-d511-4098-a45a-6b36c610ddaf
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4028744974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4028744974
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1571952348
Short name	T152
Test name
Test status
Simulation time	44966683 ps
CPU time	1.01 seconds
Started	Jan 03 12:22:42 PM PST 24
Finished	Jan 03 12:22:45 PM PST 24
Peak memory	201520 kb
Host	smart-8ae92388-9561-4457-8d5b-572480bf32ad
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571952348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c sr_outstanding.1571952348
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.4156645822
Short name	T32
Test name
Test status
Simulation time	29841428 ps
CPU time	0.61 seconds
Started	Jan 03 12:28:57 PM PST 24
Finished	Jan 03 12:29:24 PM PST 24
Peak memory	200400 kb
Host	smart-7cad63d4-79b4-4cd5-92bd-3b2445dda5d7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4156645822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4156645822
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.384616639
Short name	T47
Test name
Test status
Simulation time	20674192 ps
CPU time	0.64 seconds
Started	Jan 03 12:27:26 PM PST 24
Finished	Jan 03 12:27:33 PM PST 24
Peak memory	200648 kb
Host	smart-c0a4e1b9-5c65-4bd6-afce-c92a27e7f362
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=384616639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.384616639
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.2170558958
Short name	T134
Test name
Test status
Simulation time	24243257 ps
CPU time	0.64 seconds
Started	Jan 03 12:23:55 PM PST 24
Finished	Jan 03 12:23:56 PM PST 24
Peak memory	200700 kb
Host	smart-e2f610fd-db98-4250-8a4f-e93dc2d82c9c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2170558958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2170558958
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2851085260
Short name	T143
Test name
Test status
Simulation time	33496895 ps
CPU time	0.66 seconds
Started	Jan 03 12:30:22 PM PST 24
Finished	Jan 03 12:31:17 PM PST 24
Peak memory	199820 kb
Host	smart-56748d0d-d495-4ba6-b694-5bd0b57bca1f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2851085260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2851085260
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3050938976
Short name	T151
Test name
Test status
Simulation time	22727142 ps
CPU time	0.6 seconds
Started	Jan 03 12:28:29 PM PST 24
Finished	Jan 03 12:28:42 PM PST 24
Peak memory	200636 kb
Host	smart-e2b59af2-d321-4727-b65f-8ee1e3f8d0ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3050938976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3050938976
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2673346113
Short name	T110
Test name
Test status
Simulation time	23469553 ps
CPU time	0.63 seconds
Started	Jan 03 12:28:29 PM PST 24
Finished	Jan 03 12:28:42 PM PST 24
Peak memory	200564 kb
Host	smart-16aa88b5-53b9-4e46-8186-e5518020b416
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2673346113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2673346113
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3403002654
Short name	T115
Test name
Test status
Simulation time	117202366 ps
CPU time	1.49 seconds
Started	Jan 03 12:26:07 PM PST 24
Finished	Jan 03 12:26:09 PM PST 24
Peak memory	209996 kb
Host	smart-6fc0286d-79a2-4d2c-b7a4-c8cb37daaf94
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403002654 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.3403002654
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2755353377
Short name	T41
Test name
Test status
Simulation time	40391622 ps
CPU time	0.79 seconds
Started	Jan 03 12:24:13 PM PST 24
Finished	Jan 03 12:24:17 PM PST 24
Peak memory	201472 kb
Host	smart-8ebab7df-a578-4f4a-bdf8-772888ae14ae
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755353377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2755353377
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2700593311
Short name	T83
Test name
Test status
Simulation time	22962176 ps
CPU time	0.71 seconds
Started	Jan 03 12:30:07 PM PST 24
Finished	Jan 03 12:30:54 PM PST 24
Peak memory	198948 kb
Host	smart-68ad0530-e1af-4788-a8e5-a0e2fe887262
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2700593311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2700593311
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3220024373
Short name	T91
Test name
Test status
Simulation time	80721072 ps
CPU time	1.37 seconds
Started	Jan 03 12:24:08 PM PST 24
Finished	Jan 03 12:24:14 PM PST 24
Peak memory	201652 kb
Host	smart-e1c621ea-e14e-4886-85d6-0d94f9520776
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220024373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.3220024373
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1009524160
Short name	T117
Test name
Test status
Simulation time	327783738 ps
CPU time	3.34 seconds
Started	Jan 03 12:42:36 PM PST 24
Finished	Jan 03 12:44:02 PM PST 24
Peak memory	201696 kb
Host	smart-af7e336b-8b87-4eac-909f-b54fab9acdb6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1009524160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1009524160
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1545263035
Short name	T42
Test name
Test status
Simulation time	194929338 ps
CPU time	2.33 seconds
Started	Jan 03 12:41:44 PM PST 24
Finished	Jan 03 12:43:18 PM PST 24
Peak memory	201700 kb
Host	smart-e6c9189a-b876-4cfc-8de5-eefb20e50ea3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1545263035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1545263035
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3198328657
Short name	T89
Test name
Test status
Simulation time	56665190 ps
CPU time	2.06 seconds
Started	Jan 03 12:27:30 PM PST 24
Finished	Jan 03 12:27:37 PM PST 24
Peak memory	209032 kb
Host	smart-15e87380-60d4-4562-828f-c441c33fa116
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198328657 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3198328657
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.143467615
Short name	T9
Test name
Test status
Simulation time	38997105 ps
CPU time	0.8 seconds
Started	Jan 03 12:30:07 PM PST 24
Finished	Jan 03 12:30:54 PM PST 24
Peak memory	200208 kb
Host	smart-b0be722e-152d-481a-b672-886d7e66b072
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143467615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.143467615
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1991962245
Short name	T100
Test name
Test status
Simulation time	25796618 ps
CPU time	0.6 seconds
Started	Jan 03 12:29:28 PM PST 24
Finished	Jan 03 12:30:01 PM PST 24
Peak memory	200248 kb
Host	smart-925beeef-b891-494d-99c3-79923de4205f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1991962245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1991962245
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4281971439
Short name	T97
Test name
Test status
Simulation time	32145669 ps
CPU time	0.89 seconds
Started	Jan 03 12:29:17 PM PST 24
Finished	Jan 03 12:29:46 PM PST 24
Peak memory	201080 kb
Host	smart-c628718c-fb03-432f-a479-7714c9a92c9d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281971439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.4281971439
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.769115136
Short name	T17
Test name
Test status
Simulation time	59679147 ps
CPU time	1.65 seconds
Started	Jan 03 12:25:22 PM PST 24
Finished	Jan 03 12:25:25 PM PST 24
Peak memory	201628 kb
Host	smart-3fed007e-018b-4da2-9616-188140548a02
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=769115136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.769115136
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2774410356
Short name	T74
Test name
Test status
Simulation time	295712343 ps
CPU time	2.73 seconds
Started	Jan 03 12:30:21 PM PST 24
Finished	Jan 03 12:31:18 PM PST 24
Peak memory	201316 kb
Host	smart-43bb2965-12fd-4900-8d98-221a00f83cb5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2774410356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2774410356
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3941108950
Short name	T66
Test name
Test status
Simulation time	42523332 ps
CPU time	0.97 seconds
Started	Jan 03 12:27:48 PM PST 24
Finished	Jan 03 12:27:51 PM PST 24
Peak memory	201512 kb
Host	smart-d2f02a23-682e-4df0-b215-61e0d31885f6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941108950 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.3941108950
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3368352750
Short name	T137
Test name
Test status
Simulation time	65587161 ps
CPU time	0.79 seconds
Started	Jan 03 12:29:44 PM PST 24
Finished	Jan 03 12:30:25 PM PST 24
Peak memory	201028 kb
Host	smart-cfd1acc6-8c7e-4014-8dab-a22b4dbc6c5e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368352750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3368352750
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1771074619
Short name	T124
Test name
Test status
Simulation time	23358860 ps
CPU time	0.6 seconds
Started	Jan 03 12:29:38 PM PST 24
Finished	Jan 03 12:30:16 PM PST 24
Peak memory	200396 kb
Host	smart-b5def2c4-1f18-4441-97e2-396dc14798f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1771074619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1771074619
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4050872
Short name	T118
Test name
Test status
Simulation time	122305596 ps
CPU time	1.36 seconds
Started	Jan 03 12:27:49 PM PST 24
Finished	Jan 03 12:27:53 PM PST 24
Peak memory	201384 kb
Host	smart-ec2f5e29-3649-4ab4-bee3-0825789103c4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_ outstanding.4050872
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.158363252
Short name	T146
Test name
Test status
Simulation time	280158567 ps
CPU time	3.16 seconds
Started	Jan 03 12:24:49 PM PST 24
Finished	Jan 03 12:24:53 PM PST 24
Peak memory	201708 kb
Host	smart-f87f6320-37ee-43ad-a0a0-6af66cdeccc1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=158363252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.158363252
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2099265591
Short name	T123
Test name
Test status
Simulation time	262236475 ps
CPU time	2.45 seconds
Started	Jan 03 12:27:25 PM PST 24
Finished	Jan 03 12:27:33 PM PST 24
Peak memory	201348 kb
Host	smart-ac02e0ab-157e-4439-bca1-772159138501
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2099265591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2099265591
Directory	/workspace/7.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3773673366
Short name	T149
Test name
Test status
Simulation time	60613333 ps
CPU time	1.26 seconds
Started	Jan 03 12:24:42 PM PST 24
Finished	Jan 03 12:24:44 PM PST 24
Peak memory	201556 kb
Host	smart-ddfcda10-2902-44be-9787-d81e3000ad33
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773673366 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.3773673366
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.299746217
Short name	T51
Test name
Test status
Simulation time	60392847 ps
CPU time	1.02 seconds
Started	Jan 03 12:42:14 PM PST 24
Finished	Jan 03 12:43:38 PM PST 24
Peak memory	201760 kb
Host	smart-4c75af2d-5d2f-4ed5-8370-fb8bfcfbd632
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299746217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.299746217
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2943711668
Short name	T64
Test name
Test status
Simulation time	132040766 ps
CPU time	1.35 seconds
Started	Jan 03 12:22:42 PM PST 24
Finished	Jan 03 12:22:44 PM PST 24
Peak memory	201600 kb
Host	smart-1b513374-6330-49fb-b1c0-234f1280fe06
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943711668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.2943711668
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.893012501
Short name	T119
Test name
Test status
Simulation time	311798536 ps
CPU time	2.85 seconds
Started	Jan 03 12:27:49 PM PST 24
Finished	Jan 03 12:27:54 PM PST 24
Peak memory	201516 kb
Host	smart-67b95526-d146-499d-8701-9a338bd51475
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=893012501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.893012501
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2859475145
Short name	T59
Test name
Test status
Simulation time	41763703 ps
CPU time	0.92 seconds
Started	Jan 03 12:28:42 PM PST 24
Finished	Jan 03 12:29:05 PM PST 24
Peak memory	201652 kb
Host	smart-5ca73f5f-2981-4ae0-8ae2-3ca80a97abc5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859475145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2859475145
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2677124671
Short name	T113
Test name
Test status
Simulation time	21155680 ps
CPU time	0.65 seconds
Started	Jan 03 12:23:42 PM PST 24
Finished	Jan 03 12:23:44 PM PST 24
Peak memory	200304 kb
Host	smart-4efba99e-cda0-4ecb-b7c4-19747a05b019
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2677124671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2677124671
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.602505978
Short name	T65
Test name
Test status
Simulation time	88290349 ps
CPU time	1.04 seconds
Started	Jan 03 12:29:33 PM PST 24
Finished	Jan 03 12:30:09 PM PST 24
Peak memory	201200 kb
Host	smart-dc0e2087-bff4-4286-8d47-d7273301bc8b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602505978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_cs r_outstanding.602505978
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1102829391
Short name	T75
Test name
Test status
Simulation time	241447359 ps
CPU time	3.74 seconds
Started	Jan 03 12:30:23 PM PST 24
Finished	Jan 03 12:31:22 PM PST 24
Peak memory	201248 kb
Host	smart-56ce4b49-318f-45d5-80ab-c06b1da88a64
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1102829391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1102829391
Directory	/workspace/9.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/0.usbdev_sec_cm.1748648281
Short name	T4
Test name
Test status
Simulation time	180244861 ps
CPU time	0.94 seconds
Started	Jan 03 12:30:01 PM PST 24
Finished	Jan 03 12:30:47 PM PST 24
Peak memory	220812 kb
Host	smart-052b2ddc-f270-47af-96f3-5f13a3947e09
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1748648281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1748648281
Directory	/workspace/0.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.1290740021
Short name	T5
Test name
Test status
Simulation time	182816994 ps
CPU time	1.06 seconds
Started	Jan 03 12:25:31 PM PST 24
Finished	Jan 03 12:25:33 PM PST 24
Peak memory	222180 kb
Host	smart-6a72beb1-fcfe-4b86-822a-23b3ccc74706
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1290740021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1290740021
Directory	/workspace/3.usbdev_sec_cm/latest