Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	17	0	17	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	286	1		T31	5		T11	2		T12	2
all_pins[1]	286	1		T31	5		T11	2		T12	2
all_pins[2]	286	1		T31	5		T11	2		T12	2
all_pins[3]	286	1		T31	5		T11	2		T12	2
all_pins[4]	286	1		T31	5		T11	2		T12	2
all_pins[5]	286	1		T31	5		T11	2		T12	2
all_pins[6]	286	1		T31	5		T11	2		T12	2
all_pins[7]	286	1		T31	5		T11	2		T12	2
all_pins[8]	286	1		T31	5		T11	2		T12	2
all_pins[9]	286	1		T31	5		T11	2		T12	2
all_pins[10]	286	1		T31	5		T11	2		T12	2
all_pins[11]	286	1		T31	5		T11	2		T12	2
all_pins[12]	286	1		T31	5		T11	2		T12	2
all_pins[13]	286	1		T31	5		T11	2		T12	2
all_pins[14]	286	1		T31	5		T11	2		T12	2
all_pins[15]	286	1		T31	5		T11	2		T12	2
all_pins[16]	286	1		T31	5		T11	2		T12	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4012	1		T31	68		T11	34		T12	34
values[0x1]	850	1		T31	17		T32	28		T22	12
transitions[0x0=>0x1]	633	1		T31	15		T32	18		T22	10
transitions[0x1=>0x0]	642	1		T31	15		T32	19		T22	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	226	1		T31	5		T11	2		T12	2
all_pins[0]	values[0x1]	60	1		T32	1		T33	2		T47	3
all_pins[0]	transitions[0x0=>0x1]	46	1		T32	1		T33	2		T47	3
all_pins[0]	transitions[0x1=>0x0]	35	1		T31	3		T32	1		T22	3
all_pins[1]	values[0x0]	237	1		T31	2		T11	2		T12	2
all_pins[1]	values[0x1]	49	1		T31	3		T32	1		T22	3
all_pins[1]	transitions[0x0=>0x1]	42	1		T31	3		T22	3		T47	3
all_pins[1]	transitions[0x1=>0x0]	41	1		T32	2		T22	1		T33	2
all_pins[2]	values[0x0]	238	1		T31	5		T11	2		T12	2
all_pins[2]	values[0x1]	48	1		T32	3		T22	1		T33	2
all_pins[2]	transitions[0x0=>0x1]	38	1		T32	3		T22	1		T33	2
all_pins[2]	transitions[0x1=>0x0]	37	1		T33	1		T34	1		T47	2
all_pins[3]	values[0x0]	239	1		T31	5		T11	2		T12	2
all_pins[3]	values[0x1]	47	1		T33	1		T34	2		T47	2
all_pins[3]	transitions[0x0=>0x1]	39	1		T33	1		T34	1		T47	2
all_pins[3]	transitions[0x1=>0x0]	39	1		T31	2		T32	1		T34	4
all_pins[4]	values[0x0]	239	1		T31	3		T11	2		T12	2
all_pins[4]	values[0x1]	47	1		T31	2		T32	1		T34	5
all_pins[4]	transitions[0x0=>0x1]	34	1		T31	2		T32	1		T34	4
all_pins[4]	transitions[0x1=>0x0]	50	1		T32	4		T22	2		T33	3
all_pins[5]	values[0x0]	223	1		T31	5		T11	2		T12	2
all_pins[5]	values[0x1]	63	1		T32	4		T22	2		T33	3
all_pins[5]	transitions[0x0=>0x1]	45	1		T32	1		T33	3		T34	1
all_pins[5]	transitions[0x1=>0x0]	25	1		T34	2		T78	2		T84	1
all_pins[6]	values[0x0]	243	1		T31	5		T11	2		T12	2
all_pins[6]	values[0x1]	43	1		T32	3		T22	2		T34	2
all_pins[6]	transitions[0x0=>0x1]	35	1		T32	2		T22	2		T78	2
all_pins[6]	transitions[0x1=>0x0]	32	1		T33	2		T47	2		T71	1
all_pins[7]	values[0x0]	246	1		T31	5		T11	2		T12	2
all_pins[7]	values[0x1]	40	1		T32	1		T33	2		T34	2
all_pins[7]	transitions[0x0=>0x1]	28	1		T33	2		T47	2		T71	1
all_pins[7]	transitions[0x1=>0x0]	47	1		T31	2		T32	3		T34	2
all_pins[8]	values[0x0]	227	1		T31	3		T11	2		T12	2
all_pins[8]	values[0x1]	59	1		T31	2		T32	4		T34	4
all_pins[8]	transitions[0x0=>0x1]	34	1		T32	4		T34	4		T47	1
all_pins[8]	transitions[0x1=>0x0]	30	1		T31	1		T33	1		T34	1
all_pins[9]	values[0x0]	231	1		T31	2		T11	2		T12	2
all_pins[9]	values[0x1]	55	1		T31	3		T33	1		T34	1
all_pins[9]	transitions[0x0=>0x1]	47	1		T31	3		T34	1		T47	1
all_pins[9]	transitions[0x1=>0x0]	35	1		T32	1		T33	2		T34	2
all_pins[10]	values[0x0]	243	1		T31	5		T11	2		T12	2
all_pins[10]	values[0x1]	43	1		T32	1		T33	3		T34	2
all_pins[10]	transitions[0x0=>0x1]	39	1		T32	1		T33	3		T34	2
all_pins[10]	transitions[0x1=>0x0]	40	1		T31	2		T32	3		T34	1
all_pins[11]	values[0x0]	242	1		T31	3		T11	2		T12	2
all_pins[11]	values[0x1]	44	1		T31	2		T32	3		T34	1
all_pins[11]	transitions[0x0=>0x1]	35	1		T31	2		T32	3		T34	1
all_pins[11]	transitions[0x1=>0x0]	49	1		T31	2		T32	1		T33	4
all_pins[12]	values[0x0]	228	1		T31	3		T11	2		T12	2
all_pins[12]	values[0x1]	58	1		T31	2		T32	1		T33	4
all_pins[12]	transitions[0x0=>0x1]	37	1		T31	2		T34	1		T47	1
all_pins[12]	transitions[0x1=>0x0]	42	1		T31	2		T32	1		T22	1
all_pins[13]	values[0x0]	223	1		T31	3		T11	2		T12	2
all_pins[13]	values[0x1]	63	1		T31	2		T32	2		T22	1
all_pins[13]	transitions[0x0=>0x1]	51	1		T31	2		T32	1		T22	1
all_pins[13]	transitions[0x1=>0x0]	15	1		T34	2		T47	1		T85	1
all_pins[14]	values[0x0]	259	1		T31	5		T11	2		T12	2
all_pins[14]	values[0x1]	27	1		T32	1		T33	3		T34	2
all_pins[14]	transitions[0x0=>0x1]	18	1		T32	1		T33	3		T34	2
all_pins[14]	transitions[0x1=>0x0]	41	1		T32	1		T22	3		T78	2
all_pins[15]	values[0x0]	236	1		T31	5		T11	2		T12	2
all_pins[15]	values[0x1]	50	1		T32	1		T22	3		T47	1
all_pins[15]	transitions[0x0=>0x1]	33	1		T22	3		T47	1		T78	2
all_pins[15]	transitions[0x1=>0x0]	37	1		T31	1		T34	1		T47	4
all_pins[16]	values[0x0]	232	1		T31	4		T11	2		T12	2
all_pins[16]	values[0x1]	54	1		T31	1		T32	1		T34	1
all_pins[16]	transitions[0x0=>0x1]	32	1		T31	1		T34	1		T47	2
all_pins[16]	transitions[0x1=>0x0]	47	1		T32	1		T33	2		T47	1