Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	212	1		T31	4		T32	7		T22	4
all_values[1]	212	1		T31	4		T32	7		T22	4
all_values[2]	212	1		T31	4		T32	7		T22	4
all_values[3]	212	1		T31	4		T32	7		T22	4
all_values[4]	212	1		T31	4		T32	7		T22	4
all_values[5]	212	1		T31	4		T32	7		T22	4
all_values[6]	212	1		T31	4		T32	7		T22	4
all_values[7]	212	1		T31	4		T32	7		T22	4
all_values[8]	212	1		T31	4		T32	7		T22	4
all_values[9]	212	1		T31	4		T32	7		T22	4
all_values[10]	212	1		T31	4		T32	7		T22	4
all_values[11]	212	1		T31	4		T32	7		T22	4
all_values[12]	212	1		T31	4		T32	7		T22	4
all_values[13]	212	1		T31	4		T32	7		T22	4
all_values[14]	212	1		T31	4		T32	7		T22	4
all_values[15]	212	1		T31	4		T32	7		T22	4
all_values[16]	212	1		T31	4		T32	7		T22	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1904	1		T31	40		T32	61		T22	39
auto[1]	1700	1		T31	28		T32	58		T22	29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	675	1		T31	19		T32	18		T22	30
auto[1]	2929	1		T31	49		T32	101		T22	38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2124	1		T31	46		T32	67		T22	51
auto[1]	1480	1		T31	22		T32	52		T22	17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	22	1		T31	1		T22	1		T78	1
all_values[0]	auto[0]	auto[0]	auto[1]	34	1		T31	1		T32	3		T34	2
all_values[0]	auto[0]	auto[1]	auto[0]	21	1		T31	1		T22	3		T33	1
all_values[0]	auto[0]	auto[1]	auto[1]	48	1		T32	1		T33	1		T47	2
all_values[0]	auto[1]	auto[0]	auto[1]	36	1		T32	1		T34	5		T47	2
all_values[0]	auto[1]	auto[1]	auto[1]	51	1		T31	1		T32	2		T33	2
all_values[1]	auto[0]	auto[0]	auto[0]	21	1		T32	1		T34	1		T78	2
all_values[1]	auto[0]	auto[0]	auto[1]	36	1		T31	1		T32	2		T34	1
all_values[1]	auto[0]	auto[1]	auto[0]	26	1		T32	2		T33	1		T71	1
all_values[1]	auto[0]	auto[1]	auto[1]	43	1		T31	1		T32	1		T22	2
all_values[1]	auto[1]	auto[0]	auto[1]	47	1		T31	2		T22	1		T34	1
all_values[1]	auto[1]	auto[1]	auto[1]	39	1		T32	1		T22	1		T33	1
all_values[2]	auto[0]	auto[0]	auto[0]	13	1		T22	1		T34	1		T78	1
all_values[2]	auto[0]	auto[0]	auto[1]	55	1		T31	2		T32	3		T22	1
all_values[2]	auto[0]	auto[1]	auto[0]	20	1		T33	2		T78	1		T85	1
all_values[2]	auto[0]	auto[1]	auto[1]	28	1		T33	1		T71	1		T84	1
all_values[2]	auto[1]	auto[0]	auto[1]	50	1		T31	2		T22	1		T34	1
all_values[2]	auto[1]	auto[1]	auto[1]	46	1		T32	4		T22	1		T33	1
all_values[3]	auto[0]	auto[0]	auto[0]	28	1		T31	1		T32	5		T33	1
all_values[3]	auto[0]	auto[0]	auto[1]	40	1		T31	1		T22	1		T33	1
all_values[3]	auto[0]	auto[1]	auto[0]	7	1		T32	2		T86	1		T87	1
all_values[3]	auto[0]	auto[1]	auto[1]	47	1		T31	1		T22	2		T34	1
all_values[3]	auto[1]	auto[0]	auto[1]	46	1		T22	1		T33	2		T47	1
all_values[3]	auto[1]	auto[1]	auto[1]	44	1		T31	1		T34	4		T47	2
all_values[4]	auto[0]	auto[0]	auto[0]	22	1		T31	2		T22	2		T78	1
all_values[4]	auto[0]	auto[0]	auto[1]	43	1		T32	2		T33	1		T47	4
all_values[4]	auto[0]	auto[1]	auto[0]	23	1		T22	2		T33	1		T47	1
all_values[4]	auto[0]	auto[1]	auto[1]	39	1		T31	1		T32	2		T34	2
all_values[4]	auto[1]	auto[0]	auto[1]	40	1		T31	1		T32	1		T33	1
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T32	2		T33	1		T34	3
all_values[5]	auto[0]	auto[0]	auto[0]	19	1		T31	1		T33	1		T34	1
all_values[5]	auto[0]	auto[0]	auto[1]	41	1		T31	1		T32	1		T34	1
all_values[5]	auto[0]	auto[1]	auto[0]	7	1		T31	1		T79	3		T88	1
all_values[5]	auto[0]	auto[1]	auto[1]	47	1		T32	1		T22	2		T33	1
all_values[5]	auto[1]	auto[0]	auto[1]	50	1		T32	3		T22	1		T33	1
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T31	1		T32	2		T22	1
all_values[6]	auto[0]	auto[0]	auto[0]	25	1		T34	1		T47	1		T78	2
all_values[6]	auto[0]	auto[0]	auto[1]	38	1		T31	2		T47	1		T78	2
all_values[6]	auto[0]	auto[1]	auto[0]	16	1		T47	4		T78	1		T81	1
all_values[6]	auto[0]	auto[1]	auto[1]	40	1		T32	2		T22	1		T33	2
all_values[6]	auto[1]	auto[0]	auto[1]	57	1		T31	2		T32	2		T22	2
all_values[6]	auto[1]	auto[1]	auto[1]	36	1		T32	3		T22	1		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	23	1		T22	1		T34	2		T78	1
all_values[7]	auto[0]	auto[0]	auto[1]	47	1		T31	1		T32	4		T22	1
all_values[7]	auto[0]	auto[1]	auto[0]	16	1		T34	3		T78	1		T86	1
all_values[7]	auto[0]	auto[1]	auto[1]	48	1		T31	1		T33	1		T34	1
all_values[7]	auto[1]	auto[0]	auto[1]	41	1		T31	1		T32	1		T22	2
all_values[7]	auto[1]	auto[1]	auto[1]	37	1		T31	1		T32	2		T33	1
all_values[8]	auto[0]	auto[0]	auto[0]	17	1		T31	1		T22	1		T34	2
all_values[8]	auto[0]	auto[0]	auto[1]	48	1		T32	1		T33	1		T78	2
all_values[8]	auto[0]	auto[1]	auto[0]	19	1		T31	1		T22	3		T78	1
all_values[8]	auto[0]	auto[1]	auto[1]	44	1		T31	1		T32	2		T33	1
all_values[8]	auto[1]	auto[0]	auto[1]	38	1		T33	1		T34	2		T47	3
all_values[8]	auto[1]	auto[1]	auto[1]	46	1		T31	1		T32	4		T33	1
all_values[9]	auto[0]	auto[0]	auto[0]	23	1		T31	1		T22	1		T33	1
all_values[9]	auto[0]	auto[0]	auto[1]	39	1		T32	2		T22	2		T33	2
all_values[9]	auto[0]	auto[1]	auto[0]	20	1		T32	1		T34	1		T79	2
all_values[9]	auto[0]	auto[1]	auto[1]	51	1		T31	2		T32	2		T34	4
all_values[9]	auto[1]	auto[0]	auto[1]	40	1		T32	2		T22	1		T33	1
all_values[9]	auto[1]	auto[1]	auto[1]	39	1		T31	1		T34	1		T47	2
all_values[10]	auto[0]	auto[0]	auto[0]	26	1		T31	2		T32	1		T22	1
all_values[10]	auto[0]	auto[0]	auto[1]	41	1		T32	1		T22	2		T34	2
all_values[10]	auto[0]	auto[1]	auto[0]	19	1		T31	2		T71	1		T81	2
all_values[10]	auto[0]	auto[1]	auto[1]	45	1		T32	1		T33	1		T34	2
all_values[10]	auto[1]	auto[0]	auto[1]	44	1		T32	2		T22	1		T33	1
all_values[10]	auto[1]	auto[1]	auto[1]	37	1		T32	2		T33	1		T34	2
all_values[11]	auto[0]	auto[0]	auto[0]	37	1		T31	1		T32	1		T22	4
all_values[11]	auto[0]	auto[0]	auto[1]	39	1		T32	1		T33	1		T47	2
all_values[11]	auto[0]	auto[1]	auto[0]	14	1		T78	2		T80	3		T85	2
all_values[11]	auto[0]	auto[1]	auto[1]	39	1		T31	1		T32	1		T34	4
all_values[11]	auto[1]	auto[0]	auto[1]	46	1		T32	3		T33	1		T34	2
all_values[11]	auto[1]	auto[1]	auto[1]	37	1		T31	2		T32	1		T34	1
all_values[12]	auto[0]	auto[0]	auto[0]	20	1		T78	1		T71	2		T84	1
all_values[12]	auto[0]	auto[0]	auto[1]	40	1		T31	1		T32	1		T34	2
all_values[12]	auto[0]	auto[1]	auto[0]	17	1		T32	2		T71	2		T82	1
all_values[12]	auto[0]	auto[1]	auto[1]	37	1		T31	1		T32	1		T22	3
all_values[12]	auto[1]	auto[0]	auto[1]	55	1		T31	1		T32	2		T22	1
all_values[12]	auto[1]	auto[1]	auto[1]	43	1		T31	1		T32	1		T33	3
all_values[13]	auto[0]	auto[0]	auto[0]	18	1		T22	1		T34	2		T84	1
all_values[13]	auto[0]	auto[0]	auto[1]	50	1		T31	2		T32	2		T34	3
all_values[13]	auto[0]	auto[1]	auto[0]	10	1		T32	1		T80	1		T72	2
all_values[13]	auto[0]	auto[1]	auto[1]	44	1		T31	1		T32	1		T22	2
all_values[13]	auto[1]	auto[0]	auto[1]	47	1		T31	1		T22	1		T34	1
all_values[13]	auto[1]	auto[1]	auto[1]	43	1		T32	3		T33	1		T47	2
all_values[14]	auto[0]	auto[0]	auto[0]	37	1		T31	3		T32	1		T22	4
all_values[14]	auto[0]	auto[0]	auto[1]	49	1		T32	1		T34	3		T47	1
all_values[14]	auto[0]	auto[1]	auto[0]	13	1		T31	1		T32	1		T81	2
all_values[14]	auto[0]	auto[1]	auto[1]	33	1		T32	1		T33	1		T47	2
all_values[14]	auto[1]	auto[0]	auto[1]	50	1		T32	1		T33	1		T34	3
all_values[14]	auto[1]	auto[1]	auto[1]	30	1		T32	2		T33	1		T34	1
all_values[15]	auto[0]	auto[0]	auto[0]	22	1		T22	1		T33	2		T71	1
all_values[15]	auto[0]	auto[0]	auto[1]	49	1		T31	2		T32	5		T34	5
all_values[15]	auto[0]	auto[1]	auto[0]	13	1		T33	2		T82	3		T79	3
all_values[15]	auto[0]	auto[1]	auto[1]	45	1		T31	1		T32	1		T22	2
all_values[15]	auto[1]	auto[0]	auto[1]	44	1		T31	1		T34	2		T47	1
all_values[15]	auto[1]	auto[1]	auto[1]	39	1		T32	1		T22	1		T47	3
all_values[16]	auto[0]	auto[0]	auto[0]	21	1		T22	2		T33	2		T34	1
all_values[16]	auto[0]	auto[0]	auto[1]	38	1		T31	1		T32	2		T33	1
all_values[16]	auto[0]	auto[1]	auto[0]	20	1		T22	2		T34	1		T83	2
all_values[16]	auto[0]	auto[1]	auto[1]	44	1		T31	1		T32	1		T47	2
all_values[16]	auto[1]	auto[0]	auto[1]	52	1		T31	1		T32	3		T33	1
all_values[16]	auto[1]	auto[1]	auto[1]	37	1		T31	1		T32	1		T34	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal