USBDEV Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: 748235cbb6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 9.770s 8.350ms 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.860s 64.449us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.170s 78.535us 17 20 85.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.630s 377.300us 4 5 80.00
V1 csr_aliasing usbdev_csr_aliasing 3.400s 327.463us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.060s 56.665us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.170s 78.535us 17 20 85.00
usbdev_csr_aliasing 3.400s 327.463us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.340s 501.638us 3 5 60.00
V1 mem_partial_access usbdev_mem_partial_access 2.070s 63.430us 5 5 100.00
V1 TOTAL 58 115 50.43
V2 in_trans usbdev_in_trans 0 0 --
V2 data_toggle_clear usbdev_data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 0 0 --
V2 wake_events usbdev_wake_events 0 0 --
V2 av_buffer usbdev_av_buffer 0 0 --
V2 rx_fifo usbdev_rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0 0 --
V2 phy_config_pinflip usbdev_phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0 0 --
V2 max_length_out_transaction usbdev_max_length_out_transaction 0 0 --
V2 max_length_in_transaction usbdev_max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 0 0 --
V2 min_length_in_transaction usbdev_min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 0 0 --
V2 random_length_in_trans usbdev_random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 0 0 --
V2 in_stall usbdev_in_stall 0 0 --
V2 out_iso usbdev_out_iso 0 0 --
V2 in_iso usbdev_in_iso 0 0 --
V2 pkt_received usbdev_pkt_received 0 0 --
V2 pkt_sent usbdev_pkt_sent 0 0 --
V2 disconnected usbdev_disconnected 0 0 --
V2 host_lost usbdev_host_lost 0 0 --
V2 link_reset usbdev_link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 0 0 --
V2 link_resume usbdev_link_resume 0 0 --
V2 av_empty usbdev_av_empty 0 0 --
V2 rx_full usbdev_rx_full 0 0 --
V2 av_overflow usbdev_av_overflow 0 0 --
V2 enable usbdev_enable 0 0 --
V2 resume_link_active usbdev_resume_link_active 0 0 --
V2 device_address usbdev_device_address 0 0 --
V2 link_in_err usbdev_link_in_err 0 0 --
V2 rx_crc_err usbdev_rx_crc_err 0 0 --
V2 rx_pid_err usbdev_rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_rx_bitstuff_err 0 0 --
V2 link_out_err usbdev_link_out_err 0 0 --
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 0 0 --
V2 in_data_stage usbdev_in_data_stage 0 0 --
V2 out_data_stage usbdev_out_data_stage 0 0 --
V2 out_status_stage usbdev_out_status_stage 0 0 --
V2 in_status_stage usbdev_in_status_stage 0 0 --
V2 endpoint_access usbdev_endpoint_access 0 0 --
V2 disable_endpoint usbdev_disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 0 0 --
V2 setup_trans_ignored usbdev_setup_trans_ignored 0 0 --
V2 nak_trans usbdev_nak_trans 0 0 --
V2 stall_trans usbdev_stall_trans 0 0 --
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_NAK usbdev_stall_priority_over_NAK 0 0 --
V2 pending_in_trans usbdev_pending_in_trans 0 0 --
V2 streaming_test usbdev_streaming_test 0 0 --
V2 max_clock_error usbdev_max_clock_error 0 0 --
V2 max_phase_error usbdev_max_phase_error 0 0 --
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake usbdev_device_timeout_missing_host_handshake 0 0 --
V2 device_timeout usbdev_device_timeout 0 0 --
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 intr_test usbdev_intr_test 0.720s 126.917us 38 50 76.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.340s 327.784us 18 20 90.00
V2 tl_d_illegal_access usbdev_tl_errors 3.340s 327.784us 18 20 90.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.860s 64.449us 5 5 100.00
usbdev_csr_rw 1.170s 78.535us 17 20 85.00
usbdev_csr_aliasing 3.400s 327.463us 5 5 100.00
usbdev_same_csr_outstanding 1.620s 335.704us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.860s 64.449us 5 5 100.00
usbdev_csr_rw 1.170s 78.535us 17 20 85.00
usbdev_csr_aliasing 3.400s 327.463us 5 5 100.00
usbdev_same_csr_outstanding 1.620s 335.704us 20 20 100.00
V2 TOTAL 76 90 84.44
V2S tl_intg_err usbdev_sec_cm 1.080s 174.274us 5 5 100.00
usbdev_tl_intg_err 4.930s 501.568us 13 20 65.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 4.930s 501.568us 13 20 65.00
V2S TOTAL 18 25 72.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.680s 6.562us 0 50 0.00
usbdev_stress_all 0.660s 0 50 0.00
TOTAL 152 330 46.06

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 3 37.50
V2 65 3 1 1.54
V2S 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
77.09 90.01 75.82 95.05 3.12 87.16 92.01 96.47

Failure Buckets

Past Results