Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	210	1		T3	5		T5	2		T7	2
all_values[1]	210	1		T3	5		T5	2		T7	2
all_values[2]	210	1		T3	5		T5	2		T7	2
all_values[3]	210	1		T3	5		T5	2		T7	2
all_values[4]	210	1		T3	5		T5	2		T7	2
all_values[5]	210	1		T3	5		T5	2		T7	2
all_values[6]	210	1		T3	5		T5	2		T7	2
all_values[7]	210	1		T3	5		T5	2		T7	2
all_values[8]	210	1		T3	5		T5	2		T7	2
all_values[9]	210	1		T3	5		T5	2		T7	2
all_values[10]	210	1		T3	5		T5	2		T7	2
all_values[11]	210	1		T3	5		T5	2		T7	2
all_values[12]	210	1		T3	5		T5	2		T7	2
all_values[13]	210	1		T3	5		T5	2		T7	2
all_values[14]	210	1		T3	5		T5	2		T7	2
all_values[15]	210	1		T3	5		T5	2		T7	2
all_values[16]	210	1		T3	5		T5	2		T7	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2070	1		T3	42		T5	34		T7	34
auto[1]	1500	1		T3	43		T27	35		T29	73

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1112	1		T3	19		T5	34		T7	34
auto[1]	2458	1		T3	66		T27	70		T29	125

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	47	1		T5	2		T7	2		T10	2
all_values[0]	auto[0]	auto[1]	71	1		T3	1		T27	1		T29	3
all_values[0]	auto[1]	auto[0]	15	1		T29	3		T28	1		T72	2
all_values[0]	auto[1]	auto[1]	77	1		T3	4		T27	4		T29	1
all_values[1]	auto[0]	auto[0]	51	1		T5	2		T7	2		T10	2
all_values[1]	auto[0]	auto[1]	78	1		T3	4		T27	5		T29	5
all_values[1]	auto[1]	auto[0]	9	1		T31	1		T67	1		T73	1
all_values[1]	auto[1]	auto[1]	72	1		T3	1		T29	3		T28	1
all_values[2]	auto[0]	auto[0]	56	1		T3	2		T5	2		T7	2
all_values[2]	auto[0]	auto[1]	68	1		T27	4		T29	3		T28	5
all_values[2]	auto[1]	auto[0]	20	1		T3	3		T72	3		T66	2
all_values[2]	auto[1]	auto[1]	66	1		T27	1		T29	5		T31	2
all_values[3]	auto[0]	auto[0]	51	1		T5	2		T7	2		T10	2
all_values[3]	auto[0]	auto[1]	71	1		T3	1		T27	4		T29	2
all_values[3]	auto[1]	auto[0]	12	1		T28	2		T30	1		T72	2
all_values[3]	auto[1]	auto[1]	76	1		T3	4		T27	1		T29	6
all_values[4]	auto[0]	auto[0]	50	1		T3	1		T5	2		T7	2
all_values[4]	auto[0]	auto[1]	76	1		T27	1		T29	1		T28	5
all_values[4]	auto[1]	auto[0]	14	1		T3	4		T29	1		T74	1
all_values[4]	auto[1]	auto[1]	70	1		T27	4		T29	5		T30	1
all_values[5]	auto[0]	auto[0]	52	1		T5	2		T7	2		T10	2
all_values[5]	auto[0]	auto[1]	55	1		T3	1		T29	3		T30	3
all_values[5]	auto[1]	auto[0]	15	1		T3	1		T28	5		T30	1
all_values[5]	auto[1]	auto[1]	88	1		T3	3		T27	5		T29	5
all_values[6]	auto[0]	auto[0]	49	1		T5	2		T7	2		T10	2
all_values[6]	auto[0]	auto[1]	80	1		T3	5		T27	4		T29	3
all_values[6]	auto[1]	auto[0]	14	1		T27	1		T28	1		T69	1
all_values[6]	auto[1]	auto[1]	67	1		T29	5		T28	3		T30	1
all_values[7]	auto[0]	auto[0]	47	1		T5	2		T7	2		T10	2
all_values[7]	auto[0]	auto[1]	61	1		T3	3		T29	1		T28	1
all_values[7]	auto[1]	auto[0]	14	1		T3	1		T30	4		T31	1
all_values[7]	auto[1]	auto[1]	88	1		T3	1		T27	5		T29	7
all_values[8]	auto[0]	auto[0]	53	1		T5	2		T7	2		T10	2
all_values[8]	auto[0]	auto[1]	68	1		T3	1		T29	6		T28	2
all_values[8]	auto[1]	auto[0]	21	1		T27	2		T30	5		T31	1
all_values[8]	auto[1]	auto[1]	68	1		T3	4		T29	2		T28	3
all_values[9]	auto[0]	auto[0]	46	1		T3	1		T5	2		T7	2
all_values[9]	auto[0]	auto[1]	73	1		T27	5		T29	1		T28	4
all_values[9]	auto[1]	auto[0]	13	1		T3	1		T29	1		T30	1
all_values[9]	auto[1]	auto[1]	78	1		T3	3		T29	5		T28	1
all_values[10]	auto[0]	auto[0]	43	1		T5	2		T7	2		T10	2
all_values[10]	auto[0]	auto[1]	76	1		T3	3		T27	4		T29	7
all_values[10]	auto[1]	auto[0]	11	1		T27	1		T66	1		T75	1
all_values[10]	auto[1]	auto[1]	80	1		T3	2		T29	1		T28	4
all_values[11]	auto[0]	auto[0]	60	1		T5	2		T7	2		T10	2
all_values[11]	auto[0]	auto[1]	69	1		T3	3		T29	5		T28	4
all_values[11]	auto[1]	auto[0]	18	1		T3	1		T27	1		T30	1
all_values[11]	auto[1]	auto[1]	63	1		T3	1		T29	3		T28	1
all_values[12]	auto[0]	auto[0]	52	1		T3	1		T5	2		T7	2
all_values[12]	auto[0]	auto[1]	68	1		T3	1		T27	3		T29	7
all_values[12]	auto[1]	auto[0]	10	1		T30	1		T31	3		T66	1
all_values[12]	auto[1]	auto[1]	80	1		T3	3		T27	2		T29	1
all_values[13]	auto[0]	auto[0]	49	1		T5	2		T7	2		T10	2
all_values[13]	auto[0]	auto[1]	77	1		T3	1		T27	1		T29	4
all_values[13]	auto[1]	auto[0]	14	1		T3	1		T28	1		T69	1
all_values[13]	auto[1]	auto[1]	70	1		T3	3		T27	4		T29	4
all_values[14]	auto[0]	auto[0]	53	1		T5	2		T7	2		T10	2
all_values[14]	auto[0]	auto[1]	71	1		T3	5		T27	3		T29	4
all_values[14]	auto[1]	auto[0]	12	1		T27	1		T72	2		T75	1
all_values[14]	auto[1]	auto[1]	74	1		T27	1		T29	4		T28	2
all_values[15]	auto[0]	auto[0]	60	1		T3	1		T5	2		T7	2
all_values[15]	auto[0]	auto[1]	72	1		T3	4		T27	3		T29	4
all_values[15]	auto[1]	auto[0]	13	1		T27	1		T31	4		T66	1
all_values[15]	auto[1]	auto[1]	65	1		T29	4		T30	2		T72	5
all_values[16]	auto[0]	auto[0]	51	1		T5	2		T7	2		T10	2
all_values[16]	auto[0]	auto[1]	66	1		T3	3		T27	4		T28	2
all_values[16]	auto[1]	auto[0]	17	1		T3	1		T29	2		T30	1
all_values[16]	auto[1]	auto[1]	76	1		T3	1		T27	1		T29	5