Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.04	90.01	75.54	95.05	3.12	87.11	92.01	96.47

Total tests in report: 125

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
53.54	53.54	67.16	67.16	59.98	59.98	76.99	76.99	0.00	0.00	73.58	73.58	68.44	68.44	28.62	28.62	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2974745797
64.60	11.06	89.04	21.88	70.70	10.72	84.73	7.74	3.12	3.12	86.64	13.06	88.93	20.49	29.00	0.37	/workspace/coverage/default/2.usbdev_sec_cm.1804781568
71.28	6.68	89.78	0.73	72.34	1.64	87.31	2.58	3.12	0.00	86.64	0.00	88.93	0.00	70.82	41.82	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.4217486343
73.72	2.44	89.82	0.04	74.05	1.71	93.55	6.24	3.12	0.00	86.90	0.26	90.16	1.23	78.44	7.62	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3054338939
74.85	1.13	89.82	0.00	74.05	0.00	94.19	0.65	3.12	0.00	86.90	0.00	90.16	0.00	85.69	7.25	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.975350215
75.71	0.86	90.20	0.38	74.16	0.10	94.19	0.00	3.12	0.00	86.90	0.00	91.80	1.64	89.59	3.90	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1822649198
76.08	0.37	90.20	0.00	74.16	0.00	94.19	0.00	3.12	0.00	86.90	0.00	91.80	0.00	92.19	2.60	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1040447832
76.39	0.31	90.22	0.02	75.26	1.10	94.84	0.65	3.12	0.00	87.11	0.22	92.01	0.20	92.19	0.00	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.959511016
76.63	0.24	90.22	0.00	75.26	0.00	94.84	0.00	3.12	0.00	87.11	0.00	92.01	0.00	93.87	1.67	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1614328741
76.76	0.13	90.22	0.00	75.26	0.00	94.84	0.00	3.12	0.00	87.11	0.00	92.01	0.00	94.80	0.93	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1953864241
76.87	0.11	90.22	0.00	75.26	0.00	94.84	0.00	3.12	0.00	87.11	0.00	92.01	0.00	95.54	0.74	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.2216912904
76.92	0.05	90.22	0.00	75.26	0.00	94.84	0.00	3.12	0.00	87.11	0.00	92.01	0.00	95.91	0.37	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2499907619
76.95	0.03	90.22	0.00	75.26	0.00	95.05	0.22	3.12	0.00	87.11	0.00	92.01	0.00	95.91	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4065879280
76.98	0.03	90.22	0.00	75.26	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.10	0.19	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3997837225
77.01	0.03	90.22	0.00	75.26	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.28	0.19	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3839652492
77.03	0.03	90.22	0.00	75.26	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.19	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3603703386
77.06	0.02	90.38	0.17	75.26	0.00	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.41719741
77.08	0.02	90.38	0.00	75.41	0.15	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/default/3.usbdev_sec_cm.2913206346
77.09	0.01	90.38	0.00	75.51	0.10	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3263771328
77.10	0.01	90.38	0.00	75.54	0.03	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	96.47	0.00	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1920130102

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3973868804
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2291347006
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3625740648
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3869782036
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3447946749
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3319562281
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.121933813
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2755053763
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1266769778
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2317610024
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.638588323
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1171476617
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2361487295
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1460111000
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2198781676
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3314707992
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.557699585
/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4281196528
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1499294698
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.15800686
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.845539607
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3633376297
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.381928202
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4162440957
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3114940043
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3774723046
/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3536887375
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.605956607
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2203170138
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3357056351
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.650377764
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2750665213
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1079850086
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1025689413
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.811801701
/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.824027290
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2179389248
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1379019244
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1591634071
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2007072040
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3386955603
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1621403372
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4155073020
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2674028255
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3731175994
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.4088005961
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.807631864
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1722923573
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4277097586
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1380704006
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3376568232
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1457868824
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4088834629
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1795526479
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4158783499
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1640829473
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2607918844
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3591848759
/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3932084281
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2171790324
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.4186938146
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4104107259
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1462531788
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1714455258
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3551524064
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1680314735
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1447278200
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2873368295
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3122760610
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.1261680008
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2456925464
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.1982650736
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.3084547744
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4019108129
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.180743369
/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1837715597
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3606320572
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1922864145
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3558736319
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.792086626
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.779383591
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3242551974
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.732671473
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.53271170
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.111352741
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2394610842
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.343902564
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.159659034
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1757966479
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.550828784
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1490693279
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3489006198
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3228099831
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3720817677
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.375830010
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.565553345
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3889738639
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1805727431
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2636987019
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.757314303
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3802284539
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2728485936
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1502440879
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.220004353
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1179607967

Total test records in report: 125

tests.html | tests1.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/3.usbdev_sec_cm.2913206346	Jan 07 12:34:26 PM PST 24	Jan 07 12:36:07 PM PST 24	150858744 ps
T2	/workspace/coverage/default/2.usbdev_sec_cm.1804781568	Jan 07 12:31:01 PM PST 24	Jan 07 12:34:11 PM PST 24	105821545 ps
T3	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3932084281	Jan 07 12:38:53 PM PST 24	Jan 07 12:40:15 PM PST 24	29289023 ps
T4	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1621403372	Jan 07 12:38:09 PM PST 24	Jan 07 12:39:22 PM PST 24	58069242 ps
T5	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3263771328	Jan 07 12:38:20 PM PST 24	Jan 07 12:39:56 PM PST 24	331505309 ps
T6	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2974745797	Jan 07 12:38:29 PM PST 24	Jan 07 12:39:36 PM PST 24	494523808 ps
T7	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3054338939	Jan 07 12:38:22 PM PST 24	Jan 07 12:39:27 PM PST 24	231738727 ps
T8	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.15800686	Jan 07 12:38:46 PM PST 24	Jan 07 12:40:29 PM PST 24	27178600 ps
T9	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4065879280	Jan 07 12:38:21 PM PST 24	Jan 07 12:39:36 PM PST 24	38520621 ps
T10	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2361487295	Jan 07 12:38:42 PM PST 24	Jan 07 12:40:13 PM PST 24	91003656 ps
T25	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.180743369	Jan 07 12:37:54 PM PST 24	Jan 07 12:39:18 PM PST 24	194271482 ps
T27	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2394610842	Jan 07 12:38:37 PM PST 24	Jan 07 12:40:13 PM PST 24	43505789 ps
T22	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2873368295	Jan 07 12:38:32 PM PST 24	Jan 07 12:39:53 PM PST 24	102361292 ps
T54	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1502440879	Jan 07 12:38:10 PM PST 24	Jan 07 12:39:22 PM PST 24	64164409 ps
T11	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2755053763	Jan 07 12:38:01 PM PST 24	Jan 07 12:39:33 PM PST 24	35256562 ps
T29	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.4217486343	Jan 07 12:38:31 PM PST 24	Jan 07 12:40:27 PM PST 24	23994229 ps
T23	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.959511016	Jan 07 12:38:24 PM PST 24	Jan 07 12:40:07 PM PST 24	148653725 ps
T55	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1920130102	Jan 07 12:38:33 PM PST 24	Jan 07 12:39:43 PM PST 24	131839169 ps
T12	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3447946749	Jan 07 12:38:33 PM PST 24	Jan 07 12:39:40 PM PST 24	81364208 ps
T56	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4277097586	Jan 07 12:38:43 PM PST 24	Jan 07 12:40:03 PM PST 24	52773269 ps
T42	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3489006198	Jan 07 12:38:09 PM PST 24	Jan 07 12:39:57 PM PST 24	35027804 ps
T13	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.159659034	Jan 07 12:38:53 PM PST 24	Jan 07 12:40:28 PM PST 24	43146680 ps
T18	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3606320572	Jan 07 12:39:02 PM PST 24	Jan 07 12:40:26 PM PST 24	168756881 ps
T19	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1822649198	Jan 07 12:38:14 PM PST 24	Jan 07 12:39:47 PM PST 24	38406162 ps
T20	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3625740648	Jan 07 12:38:22 PM PST 24	Jan 07 12:39:52 PM PST 24	30720911 ps
T21	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3386955603	Jan 07 12:38:03 PM PST 24	Jan 07 12:39:04 PM PST 24	77547699 ps
T28	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.343902564	Jan 07 12:38:03 PM PST 24	Jan 07 12:39:17 PM PST 24	58343233 ps
T14	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4155073020	Jan 07 12:38:31 PM PST 24	Jan 07 12:39:52 PM PST 24	47425251 ps
T37	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1266769778	Jan 07 12:38:40 PM PST 24	Jan 07 12:39:49 PM PST 24	44162906 ps
T38	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1025689413	Jan 07 12:38:42 PM PST 24	Jan 07 12:40:23 PM PST 24	82933616 ps
T32	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3536887375	Jan 07 12:39:03 PM PST 24	Jan 07 12:40:24 PM PST 24	284418117 ps
T39	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.807631864	Jan 07 12:39:13 PM PST 24	Jan 07 12:40:31 PM PST 24	251426668 ps
T15	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.650377764	Jan 07 12:38:40 PM PST 24	Jan 07 12:40:42 PM PST 24	229129085 ps
T30	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.53271170	Jan 07 12:38:27 PM PST 24	Jan 07 12:39:37 PM PST 24	26048139 ps
T16	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1447278200	Jan 07 12:39:00 PM PST 24	Jan 07 12:40:31 PM PST 24	89423671 ps
T17	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3558736319	Jan 07 12:38:16 PM PST 24	Jan 07 12:39:22 PM PST 24	106499727 ps
T33	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2499907619	Jan 07 12:38:35 PM PST 24	Jan 07 12:39:51 PM PST 24	172044129 ps
T58	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3357056351	Jan 07 12:38:40 PM PST 24	Jan 07 12:40:38 PM PST 24	92044230 ps
T43	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3973868804	Jan 07 12:38:32 PM PST 24	Jan 07 12:39:46 PM PST 24	164502216 ps
T31	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1614328741	Jan 07 12:38:38 PM PST 24	Jan 07 12:40:05 PM PST 24	33415063 ps
T84	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2750665213	Jan 07 12:38:22 PM PST 24	Jan 07 12:39:47 PM PST 24	33543224 ps
T34	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3633376297	Jan 07 12:38:39 PM PST 24	Jan 07 12:40:00 PM PST 24	56120477 ps
T85	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1640829473	Jan 07 12:38:33 PM PST 24	Jan 07 12:40:14 PM PST 24	83071667 ps
T72	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.975350215	Jan 07 12:38:36 PM PST 24	Jan 07 12:39:47 PM PST 24	34745180 ps
T41	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1953864241	Jan 07 12:38:22 PM PST 24	Jan 07 12:39:28 PM PST 24	224774554 ps
T86	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3802284539	Jan 07 12:38:42 PM PST 24	Jan 07 12:40:20 PM PST 24	41704697 ps
T65	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2179389248	Jan 07 12:38:26 PM PST 24	Jan 07 12:39:25 PM PST 24	24714414 ps
T40	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4281196528	Jan 07 12:38:09 PM PST 24	Jan 07 12:39:12 PM PST 24	446867368 ps
T35	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1722923573	Jan 07 12:37:56 PM PST 24	Jan 07 12:39:09 PM PST 24	89158898 ps
T44	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.638588323	Jan 07 12:38:50 PM PST 24	Jan 07 12:40:21 PM PST 24	43705404 ps
T63	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.845539607	Jan 07 12:38:43 PM PST 24	Jan 07 12:39:57 PM PST 24	37117282 ps
T45	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1171476617	Jan 07 12:38:02 PM PST 24	Jan 07 12:39:07 PM PST 24	72159206 ps
T68	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.605956607	Jan 07 12:38:19 PM PST 24	Jan 07 12:39:33 PM PST 24	37053314 ps
T69	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1490693279	Jan 07 12:38:28 PM PST 24	Jan 07 12:39:30 PM PST 24	30376944 ps
T36	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.121933813	Jan 07 12:38:21 PM PST 24	Jan 07 12:39:53 PM PST 24	58374966 ps
T87	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.220004353	Jan 07 12:38:28 PM PST 24	Jan 07 12:39:45 PM PST 24	47955522 ps
T74	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.732671473	Jan 07 12:38:22 PM PST 24	Jan 07 12:39:47 PM PST 24	24262604 ps
T66	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.3084547744	Jan 07 12:38:27 PM PST 24	Jan 07 12:39:43 PM PST 24	28354900 ps
T57	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3122760610	Jan 07 12:38:19 PM PST 24	Jan 07 12:39:21 PM PST 24	76898623 ps
T67	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3551524064	Jan 07 12:38:30 PM PST 24	Jan 07 12:39:44 PM PST 24	37947865 ps
T46	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4158783499	Jan 07 12:38:28 PM PST 24	Jan 07 12:40:06 PM PST 24	90454113 ps
T88	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.557699585	Jan 07 12:38:43 PM PST 24	Jan 07 12:40:09 PM PST 24	89704481 ps
T89	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4162440957	Jan 07 12:38:43 PM PST 24	Jan 07 12:40:02 PM PST 24	91276087 ps
T90	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3720817677	Jan 07 12:38:36 PM PST 24	Jan 07 12:39:38 PM PST 24	56278513 ps
T83	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2728485936	Jan 07 12:38:38 PM PST 24	Jan 07 12:39:41 PM PST 24	31503265 ps
T75	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.4186938146	Jan 07 12:38:30 PM PST 24	Jan 07 12:39:44 PM PST 24	26668865 ps
T79	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1922864145	Jan 07 12:38:30 PM PST 24	Jan 07 12:39:53 PM PST 24	30038552 ps
T80	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2456925464	Jan 07 12:38:11 PM PST 24	Jan 07 12:39:16 PM PST 24	23922544 ps
T91	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2291347006	Jan 07 12:38:01 PM PST 24	Jan 07 12:39:19 PM PST 24	211072328 ps
T92	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.41719741	Jan 07 12:38:49 PM PST 24	Jan 07 12:40:28 PM PST 24	150217649 ps
T71	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3603703386	Jan 07 12:38:33 PM PST 24	Jan 07 12:39:46 PM PST 24	493415204 ps
T78	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2171790324	Jan 07 12:38:23 PM PST 24	Jan 07 12:39:44 PM PST 24	23926067 ps
T47	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2198781676	Jan 07 12:38:04 PM PST 24	Jan 07 12:39:35 PM PST 24	27670671 ps
T93	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3889738639	Jan 07 12:38:31 PM PST 24	Jan 07 12:40:28 PM PST 24	48170251 ps
T73	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.757314303	Jan 07 12:38:32 PM PST 24	Jan 07 12:39:36 PM PST 24	31626399 ps
T94	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.375830010	Jan 07 12:39:04 PM PST 24	Jan 07 12:40:43 PM PST 24	50201773 ps
T76	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1040447832	Jan 07 12:38:20 PM PST 24	Jan 07 12:39:34 PM PST 24	33306847 ps
T95	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3376568232	Jan 07 12:38:28 PM PST 24	Jan 07 12:39:42 PM PST 24	310491345 ps
T48	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1795526479	Jan 07 12:38:08 PM PST 24	Jan 07 12:39:26 PM PST 24	60331252 ps
T96	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.1982650736	Jan 07 12:38:35 PM PST 24	Jan 07 12:40:23 PM PST 24	27948878 ps
T77	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1591634071	Jan 07 12:38:31 PM PST 24	Jan 07 12:40:07 PM PST 24	26804068 ps
T97	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2674028255	Jan 07 12:38:47 PM PST 24	Jan 07 12:39:59 PM PST 24	22649039 ps
T82	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3839652492	Jan 07 12:38:06 PM PST 24	Jan 07 12:39:23 PM PST 24	218123635 ps
T59	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.779383591	Jan 07 12:38:04 PM PST 24	Jan 07 12:39:18 PM PST 24	87657707 ps
T60	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3319562281	Jan 07 12:38:05 PM PST 24	Jan 07 12:39:10 PM PST 24	85347963 ps
T81	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.565553345	Jan 07 12:38:17 PM PST 24	Jan 07 12:39:20 PM PST 24	25833732 ps
T64	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2007072040	Jan 07 12:39:00 PM PST 24	Jan 07 12:40:38 PM PST 24	84268640 ps
T98	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1179607967	Jan 07 12:37:56 PM PST 24	Jan 07 12:39:12 PM PST 24	239364603 ps
T61	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3997837225	Jan 07 12:38:35 PM PST 24	Jan 07 12:39:55 PM PST 24	52218172 ps
T26	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1457868824	Jan 07 12:38:19 PM PST 24	Jan 07 12:39:23 PM PST 24	25475594 ps
T99	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3591848759	Jan 07 12:38:35 PM PST 24	Jan 07 12:40:08 PM PST 24	53270394 ps
T100	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2317610024	Jan 07 12:38:41 PM PST 24	Jan 07 12:40:16 PM PST 24	45519986 ps
T49	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1680314735	Jan 07 12:38:26 PM PST 24	Jan 07 12:40:09 PM PST 24	90482784 ps
T101	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3242551974	Jan 07 12:38:07 PM PST 24	Jan 07 12:39:20 PM PST 24	62278701 ps
T52	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3731175994	Jan 07 12:38:34 PM PST 24	Jan 07 12:39:39 PM PST 24	48591308 ps
T62	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1805727431	Jan 07 12:38:19 PM PST 24	Jan 07 12:39:34 PM PST 24	39294479 ps
T102	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.381928202	Jan 07 12:38:54 PM PST 24	Jan 07 12:40:23 PM PST 24	37117785 ps
T103	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2203170138	Jan 07 12:39:22 PM PST 24	Jan 07 12:40:54 PM PST 24	39967513 ps
T50	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4104107259	Jan 07 12:38:27 PM PST 24	Jan 07 12:39:37 PM PST 24	368179133 ps
T24	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1837715597	Jan 07 12:38:27 PM PST 24	Jan 07 12:39:37 PM PST 24	26868058 ps
T51	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1079850086	Jan 07 12:38:41 PM PST 24	Jan 07 12:39:53 PM PST 24	37439809 ps
T104	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.550828784	Jan 07 12:38:26 PM PST 24	Jan 07 12:39:48 PM PST 24	170374674 ps
T105	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.811801701	Jan 07 12:38:53 PM PST 24	Jan 07 12:40:11 PM PST 24	58026933 ps
T106	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3314707992	Jan 07 12:38:53 PM PST 24	Jan 07 12:40:25 PM PST 24	145104402 ps
T107	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1380704006	Jan 07 12:38:02 PM PST 24	Jan 07 12:39:17 PM PST 24	266207171 ps
T108	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1757966479	Jan 07 12:38:17 PM PST 24	Jan 07 12:39:21 PM PST 24	133876817 ps
T109	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4019108129	Jan 07 12:38:40 PM PST 24	Jan 07 12:40:18 PM PST 24	160324419 ps
T53	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3869782036	Jan 07 12:38:31 PM PST 24	Jan 07 12:39:37 PM PST 24	45681985 ps
T110	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2607918844	Jan 07 12:38:56 PM PST 24	Jan 07 12:40:14 PM PST 24	85831299 ps
T111	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.2216912904	Jan 07 12:38:40 PM PST 24	Jan 07 12:39:43 PM PST 24	45067745 ps
T112	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1379019244	Jan 07 12:38:17 PM PST 24	Jan 07 12:39:23 PM PST 24	46711794 ps
T113	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3774723046	Jan 07 12:38:27 PM PST 24	Jan 07 12:39:46 PM PST 24	71951464 ps
T114	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1462531788	Jan 07 12:38:07 PM PST 24	Jan 07 12:39:33 PM PST 24	87413705 ps
T70	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.824027290	Jan 07 12:38:18 PM PST 24	Jan 07 12:39:27 PM PST 24	362835347 ps
T115	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.111352741	Jan 07 12:38:13 PM PST 24	Jan 07 12:39:22 PM PST 24	30677871 ps
T116	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1714455258	Jan 07 12:38:17 PM PST 24	Jan 07 12:39:23 PM PST 24	65044581 ps
T117	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3228099831	Jan 07 12:38:46 PM PST 24	Jan 07 12:40:13 PM PST 24	126007825 ps
T118	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1460111000	Jan 07 12:38:33 PM PST 24	Jan 07 12:40:17 PM PST 24	66590894 ps
T119	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2636987019	Jan 07 12:38:20 PM PST 24	Jan 07 12:39:43 PM PST 24	29378028 ps
T120	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.1261680008	Jan 07 12:38:34 PM PST 24	Jan 07 12:39:56 PM PST 24	32542965 ps
T121	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4088834629	Jan 07 12:38:36 PM PST 24	Jan 07 12:39:38 PM PST 24	84564392 ps
T122	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.792086626	Jan 07 12:38:28 PM PST 24	Jan 07 12:39:43 PM PST 24	467735805 ps
T123	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1499294698	Jan 07 12:37:54 PM PST 24	Jan 07 12:38:58 PM PST 24	52523362 ps
T124	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3114940043	Jan 07 12:38:15 PM PST 24	Jan 07 12:39:37 PM PST 24	27339049 ps
T125	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.4088005961	Jan 07 12:38:11 PM PST 24	Jan 07 12:39:48 PM PST 24	37326890 ps

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2974745797
Short name	T6
Test name
Test status
Simulation time	494523808 ps
CPU time	2.96 seconds
Started	Jan 07 12:38:29 PM PST 24
Finished	Jan 07 12:39:36 PM PST 24
Peak memory	201552 kb
Host	smart-e2090199-5c31-4dbc-9fb1-52c4fe00df76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2974745797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2974745797
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.1804781568
Short name	T2
Test name
Test status
Simulation time	105821545 ps
CPU time	0.87 seconds
Started	Jan 07 12:31:01 PM PST 24
Finished	Jan 07 12:34:11 PM PST 24
Peak memory	220904 kb
Host	smart-6f70be90-eef1-414f-8efa-7b08cc655232
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1804781568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1804781568
Directory	/workspace/2.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.4217486343
Short name	T29
Test name
Test status
Simulation time	23994229 ps
CPU time	0.64 seconds
Started	Jan 07 12:38:31 PM PST 24
Finished	Jan 07 12:40:27 PM PST 24
Peak memory	200704 kb
Host	smart-96f2c991-d201-40c8-9db4-e7d61d2f464e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4217486343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.4217486343
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3054338939
Short name	T7
Test name
Test status
Simulation time	231738727 ps
CPU time	2.43 seconds
Started	Jan 07 12:38:22 PM PST 24
Finished	Jan 07 12:39:27 PM PST 24
Peak memory	201660 kb
Host	smart-d926297a-b429-4cc6-b253-712782ee14c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3054338939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3054338939
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.975350215
Short name	T72
Test name
Test status
Simulation time	34745180 ps
CPU time	0.65 seconds
Started	Jan 07 12:38:36 PM PST 24
Finished	Jan 07 12:39:47 PM PST 24
Peak memory	200600 kb
Host	smart-0ef3d04d-5b82-42e7-8565-633fe1fa0422
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=975350215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.975350215
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1822649198
Short name	T19
Test name
Test status
Simulation time	38406162 ps
CPU time	0.96 seconds
Started	Jan 07 12:38:14 PM PST 24
Finished	Jan 07 12:39:47 PM PST 24
Peak memory	201624 kb
Host	smart-89879679-c183-4a76-b619-c71b443de423
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822649198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1822649198
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1040447832
Short name	T76
Test name
Test status
Simulation time	33306847 ps
CPU time	0.62 seconds
Started	Jan 07 12:38:20 PM PST 24
Finished	Jan 07 12:39:34 PM PST 24
Peak memory	200636 kb
Host	smart-35ffd04a-ee03-417f-a6a0-accc14877870
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1040447832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1040447832
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.959511016
Short name	T23
Test name
Test status
Simulation time	148653725 ps
CPU time	0.88 seconds
Started	Jan 07 12:38:24 PM PST 24
Finished	Jan 07 12:40:07 PM PST 24
Peak memory	201364 kb
Host	smart-850b57ec-38c6-4759-966a-f0a09e461a88
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959511016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.959511016
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1614328741
Short name	T31
Test name
Test status
Simulation time	33415063 ps
CPU time	0.63 seconds
Started	Jan 07 12:38:38 PM PST 24
Finished	Jan 07 12:40:05 PM PST 24
Peak memory	200660 kb
Host	smart-7b28de26-7b3a-462c-977f-99d82fc903d7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1614328741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1614328741
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1953864241
Short name	T41
Test name
Test status
Simulation time	224774554 ps
CPU time	3.9 seconds
Started	Jan 07 12:38:22 PM PST 24
Finished	Jan 07 12:39:28 PM PST 24
Peak memory	201612 kb
Host	smart-3b967747-65eb-425d-bf2f-763f6b93bde4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1953864241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1953864241
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.2216912904
Short name	T111
Test name
Test status
Simulation time	45067745 ps
CPU time	0.65 seconds
Started	Jan 07 12:38:40 PM PST 24
Finished	Jan 07 12:39:43 PM PST 24
Peak memory	200640 kb
Host	smart-1e0b4006-81fe-41bb-acd4-153495fc252f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2216912904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2216912904
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2499907619
Short name	T33
Test name
Test status
Simulation time	172044129 ps
CPU time	2.38 seconds
Started	Jan 07 12:38:35 PM PST 24
Finished	Jan 07 12:39:51 PM PST 24
Peak memory	201660 kb
Host	smart-46a0d670-2a4c-4cf3-b16b-e08890e04993
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2499907619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2499907619
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4065879280
Short name	T9
Test name
Test status
Simulation time	38520621 ps
CPU time	0.68 seconds
Started	Jan 07 12:38:21 PM PST 24
Finished	Jan 07 12:39:36 PM PST 24
Peak memory	201364 kb
Host	smart-fa822024-0b97-47bc-af73-84730bd6c3d5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065879280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.4065879280
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3997837225
Short name	T61
Test name
Test status
Simulation time	52218172 ps
CPU time	1.33 seconds
Started	Jan 07 12:38:35 PM PST 24
Finished	Jan 07 12:39:55 PM PST 24
Peak memory	209860 kb
Host	smart-d46d20b6-e8e1-4f17-98e3-021c11b37380
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997837225 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.3997837225
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3839652492
Short name	T82
Test name
Test status
Simulation time	218123635 ps
CPU time	2.47 seconds
Started	Jan 07 12:38:06 PM PST 24
Finished	Jan 07 12:39:23 PM PST 24
Peak memory	201616 kb
Host	smart-474194ed-a34a-4747-bcbd-63113f89c129
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3839652492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3839652492
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3603703386
Short name	T71
Test name
Test status
Simulation time	493415204 ps
CPU time	4.56 seconds
Started	Jan 07 12:38:33 PM PST 24
Finished	Jan 07 12:39:46 PM PST 24
Peak memory	201612 kb
Host	smart-0b7e85c1-1de4-4f08-aed1-19f470a680c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3603703386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3603703386
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.41719741
Short name	T92
Test name
Test status
Simulation time	150217649 ps
CPU time	1.72 seconds
Started	Jan 07 12:38:49 PM PST 24
Finished	Jan 07 12:40:28 PM PST 24
Peak memory	201748 kb
Host	smart-7636be1a-b524-4c35-bffd-d87febeaa942
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=41719741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.41719741
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.2913206346
Short name	T1
Test name
Test status
Simulation time	150858744 ps
CPU time	1.01 seconds
Started	Jan 07 12:34:26 PM PST 24
Finished	Jan 07 12:36:07 PM PST 24
Peak memory	220000 kb
Host	smart-3688c836-ded7-4a13-9ac3-234a1a7a1502
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2913206346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2913206346
Directory	/workspace/3.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3263771328
Short name	T5
Test name
Test status
Simulation time	331505309 ps
CPU time	3.26 seconds
Started	Jan 07 12:38:20 PM PST 24
Finished	Jan 07 12:39:56 PM PST 24
Peak memory	201616 kb
Host	smart-e85fea64-157f-4468-84f3-04b5a64477d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3263771328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3263771328
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1920130102
Short name	T55
Test name
Test status
Simulation time	131839169 ps
CPU time	1.47 seconds
Started	Jan 07 12:38:33 PM PST 24
Finished	Jan 07 12:39:43 PM PST 24
Peak memory	201556 kb
Host	smart-a858aa0a-f5f0-438f-a7c8-f263040470a5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920130102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.1920130102
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3973868804
Short name	T43
Test name
Test status
Simulation time	164502216 ps
CPU time	1.92 seconds
Started	Jan 07 12:38:32 PM PST 24
Finished	Jan 07 12:39:46 PM PST 24
Peak memory	201600 kb
Host	smart-cd754f0f-30fb-4803-a8aa-01f2aed719fd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973868804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3973868804
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2291347006
Short name	T91
Test name
Test status
Simulation time	211072328 ps
CPU time	4.5 seconds
Started	Jan 07 12:38:01 PM PST 24
Finished	Jan 07 12:39:19 PM PST 24
Peak memory	201560 kb
Host	smart-73d89be7-1ab4-49eb-ab6a-628a3d15e5b6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291347006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2291347006
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3625740648
Short name	T20
Test name
Test status
Simulation time	30720911 ps
CPU time	0.81 seconds
Started	Jan 07 12:38:22 PM PST 24
Finished	Jan 07 12:39:52 PM PST 24
Peak memory	201412 kb
Host	smart-3d843cb9-31f8-4011-80b8-003f3fbabcd5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625740648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3625740648
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3869782036
Short name	T53
Test name
Test status
Simulation time	45681985 ps
CPU time	1.28 seconds
Started	Jan 07 12:38:31 PM PST 24
Finished	Jan 07 12:39:37 PM PST 24
Peak memory	201592 kb
Host	smart-df4f7548-6b36-4b6d-8100-a83e737f0805
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3869782036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3869782036
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3447946749
Short name	T12
Test name
Test status
Simulation time	81364208 ps
CPU time	2.15 seconds
Started	Jan 07 12:38:33 PM PST 24
Finished	Jan 07 12:39:40 PM PST 24
Peak memory	201556 kb
Host	smart-6731baea-4476-475f-8397-72f16cfd4d45
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3447946749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3447946749
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3319562281
Short name	T60
Test name
Test status
Simulation time	85347963 ps
CPU time	1.03 seconds
Started	Jan 07 12:38:05 PM PST 24
Finished	Jan 07 12:39:10 PM PST 24
Peak memory	201540 kb
Host	smart-b3d6de92-affd-4def-8a32-9c80af16772c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319562281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.3319562281
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.121933813
Short name	T36
Test name
Test status
Simulation time	58374966 ps
CPU time	1.23 seconds
Started	Jan 07 12:38:21 PM PST 24
Finished	Jan 07 12:39:53 PM PST 24
Peak memory	201608 kb
Host	smart-2e400c4f-3cc6-4724-9b2f-47d7acfef71a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=121933813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.121933813
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2755053763
Short name	T11
Test name
Test status
Simulation time	35256562 ps
CPU time	1.07 seconds
Started	Jan 07 12:38:01 PM PST 24
Finished	Jan 07 12:39:33 PM PST 24
Peak memory	217896 kb
Host	smart-a196a029-c437-4106-86bf-1036de6d92b0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755053763 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.2755053763
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1266769778
Short name	T37
Test name
Test status
Simulation time	44162906 ps
CPU time	0.81 seconds
Started	Jan 07 12:38:40 PM PST 24
Finished	Jan 07 12:39:49 PM PST 24
Peak memory	201304 kb
Host	smart-96b9609b-d3aa-4037-a22b-b8017f4e2a98
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266769778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1266769778
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2317610024
Short name	T100
Test name
Test status
Simulation time	45519986 ps
CPU time	0.65 seconds
Started	Jan 07 12:38:41 PM PST 24
Finished	Jan 07 12:40:16 PM PST 24
Peak memory	200668 kb
Host	smart-c7ada2f0-8f06-4342-9e49-db49a9cb6897
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2317610024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2317610024
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.638588323
Short name	T44
Test name
Test status
Simulation time	43705404 ps
CPU time	1.22 seconds
Started	Jan 07 12:38:50 PM PST 24
Finished	Jan 07 12:40:21 PM PST 24
Peak memory	201508 kb
Host	smart-7a707838-617c-46cd-9900-4d85b2e1f73f
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=638588323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.638588323
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1171476617
Short name	T45
Test name
Test status
Simulation time	72159206 ps
CPU time	0.79 seconds
Started	Jan 07 12:38:02 PM PST 24
Finished	Jan 07 12:39:07 PM PST 24
Peak memory	201412 kb
Host	smart-c5298b31-71c0-48eb-9fac-9ac41ef17312
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171476617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1171476617
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2361487295
Short name	T10
Test name
Test status
Simulation time	91003656 ps
CPU time	2.67 seconds
Started	Jan 07 12:38:42 PM PST 24
Finished	Jan 07 12:40:13 PM PST 24
Peak memory	201648 kb
Host	smart-eea3f426-e297-4684-9507-a9aec5925f77
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2361487295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2361487295
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1460111000
Short name	T118
Test name
Test status
Simulation time	66590894 ps
CPU time	0.93 seconds
Started	Jan 07 12:38:33 PM PST 24
Finished	Jan 07 12:40:17 PM PST 24
Peak memory	201592 kb
Host	smart-5ea06c2c-0bdb-44ed-8152-0059e2e8fb4f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460111000 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.1460111000
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2198781676
Short name	T47
Test name
Test status
Simulation time	27670671 ps
CPU time	0.79 seconds
Started	Jan 07 12:38:04 PM PST 24
Finished	Jan 07 12:39:35 PM PST 24
Peak memory	201444 kb
Host	smart-4aed85d3-9453-4ab1-9358-d4d0701db6a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198781676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2198781676
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3314707992
Short name	T106
Test name
Test status
Simulation time	145104402 ps
CPU time	1.43 seconds
Started	Jan 07 12:38:53 PM PST 24
Finished	Jan 07 12:40:25 PM PST 24
Peak memory	201584 kb
Host	smart-ce51dc40-4408-4632-a1bb-ec7bff64b022
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314707992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.3314707992
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.557699585
Short name	T88
Test name
Test status
Simulation time	89704481 ps
CPU time	2.71 seconds
Started	Jan 07 12:38:43 PM PST 24
Finished	Jan 07 12:40:09 PM PST 24
Peak memory	201656 kb
Host	smart-4931e29c-432a-4c8e-94c7-a3873273d77b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=557699585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.557699585
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4281196528
Short name	T40
Test name
Test status
Simulation time	446867368 ps
CPU time	3.21 seconds
Started	Jan 07 12:38:09 PM PST 24
Finished	Jan 07 12:39:12 PM PST 24
Peak memory	201608 kb
Host	smart-cb28116e-e151-48ba-a830-6fd5579e3f4c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4281196528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4281196528
Directory	/workspace/11.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1499294698
Short name	T123
Test name
Test status
Simulation time	52523362 ps
CPU time	1.24 seconds
Started	Jan 07 12:37:54 PM PST 24
Finished	Jan 07 12:38:58 PM PST 24
Peak memory	209968 kb
Host	smart-4913ec4f-b1a8-4aac-bc3b-74de93d43bb4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499294698 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.1499294698
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.15800686
Short name	T8
Test name
Test status
Simulation time	27178600 ps
CPU time	0.75 seconds
Started	Jan 07 12:38:46 PM PST 24
Finished	Jan 07 12:40:29 PM PST 24
Peak memory	201344 kb
Host	smart-2351fbc6-6dd5-4e53-9549-eef89b556dcc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15800686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.15800686
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.845539607
Short name	T63
Test name
Test status
Simulation time	37117282 ps
CPU time	0.98 seconds
Started	Jan 07 12:38:43 PM PST 24
Finished	Jan 07 12:39:57 PM PST 24
Peak memory	201568 kb
Host	smart-9c9b07e6-8f58-4ee7-bcda-9e0322a73c47
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845539607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_c sr_outstanding.845539607
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3633376297
Short name	T34
Test name
Test status
Simulation time	56120477 ps
CPU time	1.54 seconds
Started	Jan 07 12:38:39 PM PST 24
Finished	Jan 07 12:40:00 PM PST 24
Peak memory	201588 kb
Host	smart-74863727-3e66-42b3-af45-0334ff2b5135
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3633376297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3633376297
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.381928202
Short name	T102
Test name
Test status
Simulation time	37117785 ps
CPU time	0.95 seconds
Started	Jan 07 12:38:54 PM PST 24
Finished	Jan 07 12:40:23 PM PST 24
Peak memory	201548 kb
Host	smart-3653a374-be22-4eb5-972b-28805aa67f94
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381928202 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.381928202
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4162440957
Short name	T89
Test name
Test status
Simulation time	91276087 ps
CPU time	1.05 seconds
Started	Jan 07 12:38:43 PM PST 24
Finished	Jan 07 12:40:02 PM PST 24
Peak memory	201532 kb
Host	smart-3bb7c270-3485-4f88-8dd9-ea8962e8abb4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162440957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.4162440957
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3114940043
Short name	T124
Test name
Test status
Simulation time	27339049 ps
CPU time	0.64 seconds
Started	Jan 07 12:38:15 PM PST 24
Finished	Jan 07 12:39:37 PM PST 24
Peak memory	200632 kb
Host	smart-fdde1d5d-caa0-4130-a95c-b9d812ca2d69
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3114940043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3114940043
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3774723046
Short name	T113
Test name
Test status
Simulation time	71951464 ps
CPU time	1.99 seconds
Started	Jan 07 12:38:27 PM PST 24
Finished	Jan 07 12:39:46 PM PST 24
Peak memory	201608 kb
Host	smart-9cd80a24-35d5-4f7c-9197-28df8b314bd0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3774723046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3774723046
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3536887375
Short name	T32
Test name
Test status
Simulation time	284418117 ps
CPU time	2.66 seconds
Started	Jan 07 12:39:03 PM PST 24
Finished	Jan 07 12:40:24 PM PST 24
Peak memory	201608 kb
Host	smart-671caf7a-1874-4dc4-8a0e-a222cf7cb233
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3536887375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3536887375
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.605956607
Short name	T68
Test name
Test status
Simulation time	37053314 ps
CPU time	1.38 seconds
Started	Jan 07 12:38:19 PM PST 24
Finished	Jan 07 12:39:33 PM PST 24
Peak memory	209816 kb
Host	smart-35b0a899-bf78-4aeb-84d6-35e98d8be81d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605956607 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.605956607
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2203170138
Short name	T103
Test name
Test status
Simulation time	39967513 ps
CPU time	0.96 seconds
Started	Jan 07 12:39:22 PM PST 24
Finished	Jan 07 12:40:54 PM PST 24
Peak memory	201688 kb
Host	smart-4cae5673-4bdc-4ab6-a729-f63efc07fdb9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203170138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2203170138
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3357056351
Short name	T58
Test name
Test status
Simulation time	92044230 ps
CPU time	1.07 seconds
Started	Jan 07 12:38:40 PM PST 24
Finished	Jan 07 12:40:38 PM PST 24
Peak memory	201512 kb
Host	smart-e4d9264a-57c0-4def-9f8d-4571dbecb2d0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357056351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.3357056351
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.650377764
Short name	T15
Test name
Test status
Simulation time	229129085 ps
CPU time	2.27 seconds
Started	Jan 07 12:38:40 PM PST 24
Finished	Jan 07 12:40:42 PM PST 24
Peak memory	201584 kb
Host	smart-21fa9a21-3afd-48d3-a2b9-d8312b8144cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=650377764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.650377764
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2750665213
Short name	T84
Test name
Test status
Simulation time	33543224 ps
CPU time	0.96 seconds
Started	Jan 07 12:38:22 PM PST 24
Finished	Jan 07 12:39:47 PM PST 24
Peak memory	201580 kb
Host	smart-323e75e6-68e2-462e-9f51-881ffc2722c2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750665213 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.2750665213
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1079850086
Short name	T51
Test name
Test status
Simulation time	37439809 ps
CPU time	0.75 seconds
Started	Jan 07 12:38:41 PM PST 24
Finished	Jan 07 12:39:53 PM PST 24
Peak memory	201396 kb
Host	smart-1c96e3d6-8264-4c61-a1fb-81d513f972e0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079850086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1079850086
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1025689413
Short name	T38
Test name
Test status
Simulation time	82933616 ps
CPU time	0.98 seconds
Started	Jan 07 12:38:42 PM PST 24
Finished	Jan 07 12:40:23 PM PST 24
Peak memory	201552 kb
Host	smart-de8df906-5b16-47cd-9794-56f9e440d6c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025689413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.1025689413
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.811801701
Short name	T105
Test name
Test status
Simulation time	58026933 ps
CPU time	1.56 seconds
Started	Jan 07 12:38:53 PM PST 24
Finished	Jan 07 12:40:11 PM PST 24
Peak memory	201664 kb
Host	smart-d135f2ac-ff52-41b7-9cd9-35cc37584e9c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=811801701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.811801701
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.824027290
Short name	T70
Test name
Test status
Simulation time	362835347 ps
CPU time	2.9 seconds
Started	Jan 07 12:38:18 PM PST 24
Finished	Jan 07 12:39:27 PM PST 24
Peak memory	201612 kb
Host	smart-b918d1c1-0f2c-4a95-85ff-b556c1bc3dd8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=824027290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.824027290
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2179389248
Short name	T65
Test name
Test status
Simulation time	24714414 ps
CPU time	0.85 seconds
Started	Jan 07 12:38:26 PM PST 24
Finished	Jan 07 12:39:25 PM PST 24
Peak memory	201560 kb
Host	smart-53bcba65-a18d-4e3d-9a2b-029755a08a10
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179389248 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.2179389248
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1379019244
Short name	T112
Test name
Test status
Simulation time	46711794 ps
CPU time	0.81 seconds
Started	Jan 07 12:38:17 PM PST 24
Finished	Jan 07 12:39:23 PM PST 24
Peak memory	201420 kb
Host	smart-c9f37a65-adb0-4267-b499-266f5a57c88b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379019244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1379019244
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1591634071
Short name	T77
Test name
Test status
Simulation time	26804068 ps
CPU time	0.63 seconds
Started	Jan 07 12:38:31 PM PST 24
Finished	Jan 07 12:40:07 PM PST 24
Peak memory	200624 kb
Host	smart-3a9a07bf-ade1-4734-a882-e73a4ef7d175
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1591634071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1591634071
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2007072040
Short name	T64
Test name
Test status
Simulation time	84268640 ps
CPU time	1.04 seconds
Started	Jan 07 12:39:00 PM PST 24
Finished	Jan 07 12:40:38 PM PST 24
Peak memory	201568 kb
Host	smart-067d6517-2720-477d-a3d8-79b79b80000d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007072040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.2007072040
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3386955603
Short name	T21
Test name
Test status
Simulation time	77547699 ps
CPU time	0.96 seconds
Started	Jan 07 12:38:03 PM PST 24
Finished	Jan 07 12:39:04 PM PST 24
Peak memory	201540 kb
Host	smart-859fc1a1-63ba-4f5a-ad24-5591b92abdc1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386955603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3386955603
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1621403372
Short name	T4
Test name
Test status
Simulation time	58069242 ps
CPU time	1.25 seconds
Started	Jan 07 12:38:09 PM PST 24
Finished	Jan 07 12:39:22 PM PST 24
Peak memory	201640 kb
Host	smart-d4efb224-cb9e-430f-8409-d561e15888cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621403372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.1621403372
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4155073020
Short name	T14
Test name
Test status
Simulation time	47425251 ps
CPU time	1.35 seconds
Started	Jan 07 12:38:31 PM PST 24
Finished	Jan 07 12:39:52 PM PST 24
Peak memory	201600 kb
Host	smart-280ff6ce-9edb-40dc-83e5-73d600442132
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4155073020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.4155073020
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2674028255
Short name	T97
Test name
Test status
Simulation time	22649039 ps
CPU time	0.89 seconds
Started	Jan 07 12:38:47 PM PST 24
Finished	Jan 07 12:39:59 PM PST 24
Peak memory	201612 kb
Host	smart-6d711786-6c57-4308-89f9-1b4e57f3bb5e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674028255 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.2674028255
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3731175994
Short name	T52
Test name
Test status
Simulation time	48591308 ps
CPU time	0.85 seconds
Started	Jan 07 12:38:34 PM PST 24
Finished	Jan 07 12:39:39 PM PST 24
Peak memory	201276 kb
Host	smart-d9ab5824-03ee-4862-83c8-9c57df82b977
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731175994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3731175994
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.4088005961
Short name	T125
Test name
Test status
Simulation time	37326890 ps
CPU time	0.64 seconds
Started	Jan 07 12:38:11 PM PST 24
Finished	Jan 07 12:39:48 PM PST 24
Peak memory	200684 kb
Host	smart-dec306d1-29e8-4655-a263-cb1ead68958b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4088005961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.4088005961
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.807631864
Short name	T39
Test name
Test status
Simulation time	251426668 ps
CPU time	1.69 seconds
Started	Jan 07 12:39:13 PM PST 24
Finished	Jan 07 12:40:31 PM PST 24
Peak memory	201556 kb
Host	smart-53d98061-cc06-4ef5-ab7b-7beea6a6ebdb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807631864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_c sr_outstanding.807631864
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1722923573
Short name	T35
Test name
Test status
Simulation time	89158898 ps
CPU time	2.51 seconds
Started	Jan 07 12:37:56 PM PST 24
Finished	Jan 07 12:39:09 PM PST 24
Peak memory	201584 kb
Host	smart-68e78046-d3ce-4dcf-88b8-c9b8c0cbb316
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1722923573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1722923573
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4277097586
Short name	T56
Test name
Test status
Simulation time	52773269 ps
CPU time	0.98 seconds
Started	Jan 07 12:38:43 PM PST 24
Finished	Jan 07 12:40:03 PM PST 24
Peak memory	201512 kb
Host	smart-854eb503-e8c0-4254-902b-1445296fae58
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277097586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.4277097586
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1380704006
Short name	T107
Test name
Test status
Simulation time	266207171 ps
CPU time	2.8 seconds
Started	Jan 07 12:38:02 PM PST 24
Finished	Jan 07 12:39:17 PM PST 24
Peak memory	201620 kb
Host	smart-ef088476-2db4-4509-9e31-190e3d5fd7f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1380704006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1380704006
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3376568232
Short name	T95
Test name
Test status
Simulation time	310491345 ps
CPU time	3.39 seconds
Started	Jan 07 12:38:28 PM PST 24
Finished	Jan 07 12:39:42 PM PST 24
Peak memory	201508 kb
Host	smart-f28ecc00-e1f6-49f4-acc4-ae987310a7a6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376568232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3376568232
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1457868824
Short name	T26
Test name
Test status
Simulation time	25475594 ps
CPU time	0.66 seconds
Started	Jan 07 12:38:19 PM PST 24
Finished	Jan 07 12:39:23 PM PST 24
Peak memory	201272 kb
Host	smart-8f306f87-acba-44a5-8fd9-363b6336e5b0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457868824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1457868824
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4088834629
Short name	T121
Test name
Test status
Simulation time	84564392 ps
CPU time	1.41 seconds
Started	Jan 07 12:38:36 PM PST 24
Finished	Jan 07 12:39:38 PM PST 24
Peak memory	201676 kb
Host	smart-9d0e712a-3468-4114-8c74-557a09eb0d41
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088834629 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.4088834629
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1795526479
Short name	T48
Test name
Test status
Simulation time	60331252 ps
CPU time	0.93 seconds
Started	Jan 07 12:38:08 PM PST 24
Finished	Jan 07 12:39:26 PM PST 24
Peak memory	201760 kb
Host	smart-e1ad9c58-ed73-4e69-b1ee-4d3cbd53c9b0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795526479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1795526479
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4158783499
Short name	T46
Test name
Test status
Simulation time	90454113 ps
CPU time	1.36 seconds
Started	Jan 07 12:38:28 PM PST 24
Finished	Jan 07 12:40:06 PM PST 24
Peak memory	201580 kb
Host	smart-5742b68a-14d1-4686-b267-ef4c0107da74
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4158783499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4158783499
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1640829473
Short name	T85
Test name
Test status
Simulation time	83071667 ps
CPU time	2.11 seconds
Started	Jan 07 12:38:33 PM PST 24
Finished	Jan 07 12:40:14 PM PST 24
Peak memory	201504 kb
Host	smart-53f7bc23-c00b-4d3d-a2cd-971e5e08eaec
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1640829473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1640829473
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2607918844
Short name	T110
Test name
Test status
Simulation time	85831299 ps
CPU time	0.97 seconds
Started	Jan 07 12:38:56 PM PST 24
Finished	Jan 07 12:40:14 PM PST 24
Peak memory	201636 kb
Host	smart-03edcd01-9114-443b-b932-07d41e58e650
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607918844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c sr_outstanding.2607918844
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3591848759
Short name	T99
Test name
Test status
Simulation time	53270394 ps
CPU time	1.39 seconds
Started	Jan 07 12:38:35 PM PST 24
Finished	Jan 07 12:40:08 PM PST 24
Peak memory	201532 kb
Host	smart-fe9b4caa-2ac4-4739-918c-9ecfc3d3e46d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3591848759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3591848759
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3932084281
Short name	T3
Test name
Test status
Simulation time	29289023 ps
CPU time	0.61 seconds
Started	Jan 07 12:38:53 PM PST 24
Finished	Jan 07 12:40:15 PM PST 24
Peak memory	200672 kb
Host	smart-c9eec57b-1222-40f1-8e60-9ac4d5a74392
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3932084281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3932084281
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2171790324
Short name	T78
Test name
Test status
Simulation time	23926067 ps
CPU time	0.58 seconds
Started	Jan 07 12:38:23 PM PST 24
Finished	Jan 07 12:39:44 PM PST 24
Peak memory	200640 kb
Host	smart-e31ff4ab-9769-4206-a4f9-26d26c38c163
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2171790324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2171790324
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.4186938146
Short name	T75
Test name
Test status
Simulation time	26668865 ps
CPU time	0.62 seconds
Started	Jan 07 12:38:30 PM PST 24
Finished	Jan 07 12:39:44 PM PST 24
Peak memory	200676 kb
Host	smart-d07a763a-01dd-4511-ac2b-8cff4bcb572a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4186938146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.4186938146
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4104107259
Short name	T50
Test name
Test status
Simulation time	368179133 ps
CPU time	3.41 seconds
Started	Jan 07 12:38:27 PM PST 24
Finished	Jan 07 12:39:37 PM PST 24
Peak memory	201404 kb
Host	smart-49dbaad9-e701-4359-afeb-0053bddd5733
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104107259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.4104107259
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1462531788
Short name	T114
Test name
Test status
Simulation time	87413705 ps
CPU time	1.19 seconds
Started	Jan 07 12:38:07 PM PST 24
Finished	Jan 07 12:39:33 PM PST 24
Peak memory	209728 kb
Host	smart-2e2701d7-50ca-4208-b2a4-b74b6a2aad99
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462531788 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.1462531788
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1714455258
Short name	T116
Test name
Test status
Simulation time	65044581 ps
CPU time	1.01 seconds
Started	Jan 07 12:38:17 PM PST 24
Finished	Jan 07 12:39:23 PM PST 24
Peak memory	201612 kb
Host	smart-78bc3347-65a8-4835-8cac-19a3904f21cd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714455258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1714455258
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3551524064
Short name	T67
Test name
Test status
Simulation time	37947865 ps
CPU time	0.62 seconds
Started	Jan 07 12:38:30 PM PST 24
Finished	Jan 07 12:39:44 PM PST 24
Peak memory	200760 kb
Host	smart-2413f3eb-d744-43d7-87d0-50c9c2257c86
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3551524064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3551524064
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1680314735
Short name	T49
Test name
Test status
Simulation time	90482784 ps
CPU time	1.38 seconds
Started	Jan 07 12:38:26 PM PST 24
Finished	Jan 07 12:40:09 PM PST 24
Peak memory	201656 kb
Host	smart-04e0c786-dd0c-442d-88f9-3fc54e69622e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1680314735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1680314735
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1447278200
Short name	T16
Test name
Test status
Simulation time	89423671 ps
CPU time	2.2 seconds
Started	Jan 07 12:39:00 PM PST 24
Finished	Jan 07 12:40:31 PM PST 24
Peak memory	201544 kb
Host	smart-0b4f543b-7149-4b36-a4cc-22087190d50d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1447278200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1447278200
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2873368295
Short name	T22
Test name
Test status
Simulation time	102361292 ps
CPU time	1.08 seconds
Started	Jan 07 12:38:32 PM PST 24
Finished	Jan 07 12:39:53 PM PST 24
Peak memory	201572 kb
Host	smart-245bf155-5f81-4b29-8351-11685bf3d765
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873368295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.2873368295
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3122760610
Short name	T57
Test name
Test status
Simulation time	76898623 ps
CPU time	2.13 seconds
Started	Jan 07 12:38:19 PM PST 24
Finished	Jan 07 12:39:21 PM PST 24
Peak memory	201584 kb
Host	smart-d3cb0638-9342-4f38-9902-540e8c38d201
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3122760610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3122760610
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.1261680008
Short name	T120
Test name
Test status
Simulation time	32542965 ps
CPU time	0.64 seconds
Started	Jan 07 12:38:34 PM PST 24
Finished	Jan 07 12:39:56 PM PST 24
Peak memory	200632 kb
Host	smart-69db2d6f-9354-4b21-b723-744c55d04410
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1261680008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1261680008
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.2456925464
Short name	T80
Test name
Test status
Simulation time	23922544 ps
CPU time	0.6 seconds
Started	Jan 07 12:38:11 PM PST 24
Finished	Jan 07 12:39:16 PM PST 24
Peak memory	200644 kb
Host	smart-bdd1743d-08e4-4290-b52b-ef23d2d58d94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2456925464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2456925464
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.1982650736
Short name	T96
Test name
Test status
Simulation time	27948878 ps
CPU time	0.62 seconds
Started	Jan 07 12:38:35 PM PST 24
Finished	Jan 07 12:40:23 PM PST 24
Peak memory	200764 kb
Host	smart-3b5e0df8-df4e-471d-be3f-c09d3f702a03
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1982650736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1982650736
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.3084547744
Short name	T66
Test name
Test status
Simulation time	28354900 ps
CPU time	0.63 seconds
Started	Jan 07 12:38:27 PM PST 24
Finished	Jan 07 12:39:43 PM PST 24
Peak memory	200672 kb
Host	smart-5a5771e6-2011-4547-881b-a79a124f3602
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3084547744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3084547744
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4019108129
Short name	T109
Test name
Test status
Simulation time	160324419 ps
CPU time	1.84 seconds
Started	Jan 07 12:38:40 PM PST 24
Finished	Jan 07 12:40:18 PM PST 24
Peak memory	201684 kb
Host	smart-2c06c76c-98b4-4d59-9a04-b788166ed2b0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019108129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.4019108129
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.180743369
Short name	T25
Test name
Test status
Simulation time	194271482 ps
CPU time	4.39 seconds
Started	Jan 07 12:37:54 PM PST 24
Finished	Jan 07 12:39:18 PM PST 24
Peak memory	201596 kb
Host	smart-9693508b-5410-4a25-81fe-5197bd4cbc28
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180743369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.180743369
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1837715597
Short name	T24
Test name
Test status
Simulation time	26868058 ps
CPU time	0.67 seconds
Started	Jan 07 12:38:27 PM PST 24
Finished	Jan 07 12:39:37 PM PST 24
Peak memory	201276 kb
Host	smart-cb580a75-8e69-4d08-a7a3-9f011e1613bd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837715597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1837715597
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3606320572
Short name	T18
Test name
Test status
Simulation time	168756881 ps
CPU time	1.09 seconds
Started	Jan 07 12:39:02 PM PST 24
Finished	Jan 07 12:40:26 PM PST 24
Peak memory	201700 kb
Host	smart-9af24eed-e8d2-4585-915d-e640088e8011
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606320572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3606320572
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1922864145
Short name	T79
Test name
Test status
Simulation time	30038552 ps
CPU time	0.6 seconds
Started	Jan 07 12:38:30 PM PST 24
Finished	Jan 07 12:39:53 PM PST 24
Peak memory	200684 kb
Host	smart-87746eaf-dd1c-45fc-9922-9c491fc09aa7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1922864145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1922864145
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3558736319
Short name	T17
Test name
Test status
Simulation time	106499727 ps
CPU time	1.33 seconds
Started	Jan 07 12:38:16 PM PST 24
Finished	Jan 07 12:39:22 PM PST 24
Peak memory	201616 kb
Host	smart-7962384f-765a-498a-9475-f0f4a40b01f1
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3558736319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3558736319
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.792086626
Short name	T122
Test name
Test status
Simulation time	467735805 ps
CPU time	4.07 seconds
Started	Jan 07 12:38:28 PM PST 24
Finished	Jan 07 12:39:43 PM PST 24
Peak memory	201540 kb
Host	smart-f7096503-8c84-43e6-b173-744c3c93cd99
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=792086626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.792086626
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.779383591
Short name	T59
Test name
Test status
Simulation time	87657707 ps
CPU time	1.04 seconds
Started	Jan 07 12:38:04 PM PST 24
Finished	Jan 07 12:39:18 PM PST 24
Peak memory	201568 kb
Host	smart-7bd00ed2-5363-48db-9b06-5143f3411f64
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779383591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_cs r_outstanding.779383591
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3242551974
Short name	T101
Test name
Test status
Simulation time	62278701 ps
CPU time	1.46 seconds
Started	Jan 07 12:38:07 PM PST 24
Finished	Jan 07 12:39:20 PM PST 24
Peak memory	201616 kb
Host	smart-26df1de7-6a07-46be-ab9f-f4c764d05920
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3242551974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3242551974
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.732671473
Short name	T74
Test name
Test status
Simulation time	24262604 ps
CPU time	0.63 seconds
Started	Jan 07 12:38:22 PM PST 24
Finished	Jan 07 12:39:47 PM PST 24
Peak memory	200776 kb
Host	smart-0b96e6bc-8db6-4ebc-abe4-0539a7376417
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=732671473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.732671473
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.53271170
Short name	T30
Test name
Test status
Simulation time	26048139 ps
CPU time	0.59 seconds
Started	Jan 07 12:38:27 PM PST 24
Finished	Jan 07 12:39:37 PM PST 24
Peak memory	200696 kb
Host	smart-76f97f64-c37c-42b6-a9a6-e9cb1b683731
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=53271170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.53271170
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.111352741
Short name	T115
Test name
Test status
Simulation time	30677871 ps
CPU time	0.63 seconds
Started	Jan 07 12:38:13 PM PST 24
Finished	Jan 07 12:39:22 PM PST 24
Peak memory	200736 kb
Host	smart-423e0183-9bdf-4b2b-ab59-247a6afa48b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=111352741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.111352741
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2394610842
Short name	T27
Test name
Test status
Simulation time	43505789 ps
CPU time	0.63 seconds
Started	Jan 07 12:38:37 PM PST 24
Finished	Jan 07 12:40:13 PM PST 24
Peak memory	200660 kb
Host	smart-9e98a468-2ee3-4610-91d4-4c1b0e021daa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2394610842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2394610842
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.343902564
Short name	T28
Test name
Test status
Simulation time	58343233 ps
CPU time	0.62 seconds
Started	Jan 07 12:38:03 PM PST 24
Finished	Jan 07 12:39:17 PM PST 24
Peak memory	200732 kb
Host	smart-3f62bb31-4f20-4c0d-8bef-7606da11151b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=343902564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.343902564
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.159659034
Short name	T13
Test name
Test status
Simulation time	43146680 ps
CPU time	1.58 seconds
Started	Jan 07 12:38:53 PM PST 24
Finished	Jan 07 12:40:28 PM PST 24
Peak memory	211432 kb
Host	smart-d131d56b-27e7-4418-b65b-e86f7b81f24a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159659034 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.159659034
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1757966479
Short name	T108
Test name
Test status
Simulation time	133876817 ps
CPU time	1.31 seconds
Started	Jan 07 12:38:17 PM PST 24
Finished	Jan 07 12:39:21 PM PST 24
Peak memory	201588 kb
Host	smart-9dd104a6-c4cc-4f73-ab6b-fac8aff8e714
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757966479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.1757966479
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.550828784
Short name	T104
Test name
Test status
Simulation time	170374674 ps
CPU time	1.09 seconds
Started	Jan 07 12:38:26 PM PST 24
Finished	Jan 07 12:39:48 PM PST 24
Peak memory	201624 kb
Host	smart-99783c55-9f40-4259-b86a-caf9e4efb76d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550828784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.550828784
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1490693279
Short name	T69
Test name
Test status
Simulation time	30376944 ps
CPU time	0.62 seconds
Started	Jan 07 12:38:28 PM PST 24
Finished	Jan 07 12:39:30 PM PST 24
Peak memory	200680 kb
Host	smart-04168ed7-4401-4529-b9af-add5fcc1a32f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1490693279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1490693279
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3489006198
Short name	T42
Test name
Test status
Simulation time	35027804 ps
CPU time	0.95 seconds
Started	Jan 07 12:38:09 PM PST 24
Finished	Jan 07 12:39:57 PM PST 24
Peak memory	201668 kb
Host	smart-520ca901-34b2-416a-9a6d-a849a597a179
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489006198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.3489006198
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3228099831
Short name	T117
Test name
Test status
Simulation time	126007825 ps
CPU time	1.6 seconds
Started	Jan 07 12:38:46 PM PST 24
Finished	Jan 07 12:40:13 PM PST 24
Peak memory	201560 kb
Host	smart-3767d32e-74c4-4691-a744-2a508036d5ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3228099831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3228099831
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3720817677
Short name	T90
Test name
Test status
Simulation time	56278513 ps
CPU time	1.03 seconds
Started	Jan 07 12:38:36 PM PST 24
Finished	Jan 07 12:39:38 PM PST 24
Peak memory	201628 kb
Host	smart-12bc59c3-4928-4a22-b684-276fe02c7cbb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720817677 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.3720817677
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.375830010
Short name	T94
Test name
Test status
Simulation time	50201773 ps
CPU time	0.84 seconds
Started	Jan 07 12:39:04 PM PST 24
Finished	Jan 07 12:40:43 PM PST 24
Peak memory	201440 kb
Host	smart-3741433b-91ef-4bd2-872d-daa0277ccc41
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375830010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.375830010
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.565553345
Short name	T81
Test name
Test status
Simulation time	25833732 ps
CPU time	0.6 seconds
Started	Jan 07 12:38:17 PM PST 24
Finished	Jan 07 12:39:20 PM PST 24
Peak memory	200676 kb
Host	smart-2463387c-d4b8-44de-b15a-d08affc13327
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=565553345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.565553345
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3889738639
Short name	T93
Test name
Test status
Simulation time	48170251 ps
CPU time	1.45 seconds
Started	Jan 07 12:38:31 PM PST 24
Finished	Jan 07 12:40:28 PM PST 24
Peak memory	201648 kb
Host	smart-9fabf04c-4e41-4f01-9f94-305306c2fb4b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3889738639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3889738639
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1805727431
Short name	T62
Test name
Test status
Simulation time	39294479 ps
CPU time	0.92 seconds
Started	Jan 07 12:38:19 PM PST 24
Finished	Jan 07 12:39:34 PM PST 24
Peak memory	201708 kb
Host	smart-2e724479-4da5-4da6-9dde-f991c91691ce
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805727431 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.1805727431
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2636987019
Short name	T119
Test name
Test status
Simulation time	29378028 ps
CPU time	0.76 seconds
Started	Jan 07 12:38:20 PM PST 24
Finished	Jan 07 12:39:43 PM PST 24
Peak memory	201516 kb
Host	smart-e4ead360-d5a6-4d4e-86dd-656edcf52da1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636987019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2636987019
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.757314303
Short name	T73
Test name
Test status
Simulation time	31626399 ps
CPU time	0.6 seconds
Started	Jan 07 12:38:32 PM PST 24
Finished	Jan 07 12:39:36 PM PST 24
Peak memory	200652 kb
Host	smart-315c7caf-9835-4646-b67d-2a20718f46e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=757314303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.757314303
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3802284539
Short name	T86
Test name
Test status
Simulation time	41704697 ps
CPU time	0.96 seconds
Started	Jan 07 12:38:42 PM PST 24
Finished	Jan 07 12:40:20 PM PST 24
Peak memory	201536 kb
Host	smart-a86aa922-35a8-4505-ac68-86feb66f7f54
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802284539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.3802284539
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2728485936
Short name	T83
Test name
Test status
Simulation time	31503265 ps
CPU time	1.02 seconds
Started	Jan 07 12:38:38 PM PST 24
Finished	Jan 07 12:39:41 PM PST 24
Peak memory	201612 kb
Host	smart-7ba1ca75-5a7b-4200-8bee-556d86e96058
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728485936 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.2728485936
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1502440879
Short name	T54
Test name
Test status
Simulation time	64164409 ps
CPU time	1 seconds
Started	Jan 07 12:38:10 PM PST 24
Finished	Jan 07 12:39:22 PM PST 24
Peak memory	201544 kb
Host	smart-615ba425-5996-4895-abde-596df8344830
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502440879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1502440879
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.220004353
Short name	T87
Test name
Test status
Simulation time	47955522 ps
CPU time	1.03 seconds
Started	Jan 07 12:38:28 PM PST 24
Finished	Jan 07 12:39:45 PM PST 24
Peak memory	201520 kb
Host	smart-ea305897-2a3f-4f79-9dc9-56631eb35013
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220004353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_cs r_outstanding.220004353
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1179607967
Short name	T98
Test name
Test status
Simulation time	239364603 ps
CPU time	1.71 seconds
Started	Jan 07 12:37:56 PM PST 24
Finished	Jan 07 12:39:12 PM PST 24
Peak memory	201724 kb
Host	smart-520319d8-59c3-4001-9820-ad0bd5bbd802
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1179607967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1179607967
Directory	/workspace/9.usbdev_tl_errors/latest