Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	17	0	17	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	210	1		T3	5		T5	2		T7	2
all_pins[1]	210	1		T3	5		T5	2		T7	2
all_pins[2]	210	1		T3	5		T5	2		T7	2
all_pins[3]	210	1		T3	5		T5	2		T7	2
all_pins[4]	210	1		T3	5		T5	2		T7	2
all_pins[5]	210	1		T3	5		T5	2		T7	2
all_pins[6]	210	1		T3	5		T5	2		T7	2
all_pins[7]	210	1		T3	5		T5	2		T7	2
all_pins[8]	210	1		T3	5		T5	2		T7	2
all_pins[9]	210	1		T3	5		T5	2		T7	2
all_pins[10]	210	1		T3	5		T5	2		T7	2
all_pins[11]	210	1		T3	5		T5	2		T7	2
all_pins[12]	210	1		T3	5		T5	2		T7	2
all_pins[13]	210	1		T3	5		T5	2		T7	2
all_pins[14]	210	1		T3	5		T5	2		T7	2
all_pins[15]	210	1		T3	5		T5	2		T7	2
all_pins[16]	210	1		T3	5		T5	2		T7	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2973	1		T3	66		T5	34		T7	34
values[0x1]	597	1		T3	19		T27	11		T29	34
transitions[0x0=>0x1]	442	1		T3	14		T27	9		T29	26
transitions[0x1=>0x0]	448	1		T3	14		T27	9		T29	26

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	173	1		T3	2		T5	2		T7	2
all_pins[0]	values[0x1]	37	1		T3	3		T29	1		T30	2
all_pins[0]	transitions[0x0=>0x1]	25	1		T3	2		T29	1		T72	2
all_pins[0]	transitions[0x1=>0x0]	25	1		T28	1		T30	1		T72	1
all_pins[1]	values[0x0]	173	1		T3	4		T5	2		T7	2
all_pins[1]	values[0x1]	37	1		T3	1		T28	1		T30	3
all_pins[1]	transitions[0x0=>0x1]	30	1		T3	1		T28	1		T30	3
all_pins[1]	transitions[0x1=>0x0]	28	1		T3	2		T27	1		T29	1
all_pins[2]	values[0x0]	175	1		T3	3		T5	2		T7	2
all_pins[2]	values[0x1]	35	1		T3	2		T27	1		T29	1
all_pins[2]	transitions[0x0=>0x1]	27	1		T27	1		T29	1		T72	2
all_pins[2]	transitions[0x1=>0x0]	27	1		T3	1		T27	1		T29	4
all_pins[3]	values[0x0]	175	1		T3	2		T5	2		T7	2
all_pins[3]	values[0x1]	35	1		T3	3		T27	1		T29	4
all_pins[3]	transitions[0x0=>0x1]	30	1		T3	3		T29	2		T31	1
all_pins[3]	transitions[0x1=>0x0]	27	1		T29	2		T30	1		T72	3
all_pins[4]	values[0x0]	178	1		T3	5		T5	2		T7	2
all_pins[4]	values[0x1]	32	1		T27	1		T29	4		T30	1
all_pins[4]	transitions[0x0=>0x1]	26	1		T29	4		T30	1		T72	2
all_pins[4]	transitions[0x1=>0x0]	29	1		T27	1		T30	1		T31	3
all_pins[5]	values[0x0]	175	1		T3	5		T5	2		T7	2
all_pins[5]	values[0x1]	35	1		T27	2		T30	1		T31	3
all_pins[5]	transitions[0x0=>0x1]	28	1		T27	2		T30	1		T31	2
all_pins[5]	transitions[0x1=>0x0]	28	1		T29	2		T28	2		T31	1
all_pins[6]	values[0x0]	175	1		T3	5		T5	2		T7	2
all_pins[6]	values[0x1]	35	1		T29	2		T28	2		T31	2
all_pins[6]	transitions[0x0=>0x1]	21	1		T28	2		T31	2		T72	1
all_pins[6]	transitions[0x1=>0x0]	28	1		T3	1		T27	1		T29	3
all_pins[7]	values[0x0]	168	1		T3	4		T5	2		T7	2
all_pins[7]	values[0x1]	42	1		T3	1		T27	1		T29	5
all_pins[7]	transitions[0x0=>0x1]	34	1		T3	1		T27	1		T29	5
all_pins[7]	transitions[0x1=>0x0]	14	1		T29	1		T28	2		T72	2
all_pins[8]	values[0x0]	188	1		T3	5		T5	2		T7	2
all_pins[8]	values[0x1]	22	1		T29	1		T28	2		T72	2
all_pins[8]	transitions[0x0=>0x1]	21	1		T29	1		T28	2		T72	2
all_pins[8]	transitions[0x1=>0x0]	28	1		T3	2		T29	4		T72	2
all_pins[9]	values[0x0]	181	1		T3	3		T5	2		T7	2
all_pins[9]	values[0x1]	29	1		T3	2		T29	4		T72	2
all_pins[9]	transitions[0x0=>0x1]	22	1		T3	2		T29	4		T69	1
all_pins[9]	transitions[0x1=>0x0]	27	1		T3	1		T28	1		T30	2
all_pins[10]	values[0x0]	176	1		T3	4		T5	2		T7	2
all_pins[10]	values[0x1]	34	1		T3	1		T28	1		T30	2
all_pins[10]	transitions[0x0=>0x1]	26	1		T3	1		T28	1		T30	2
all_pins[10]	transitions[0x1=>0x0]	25	1		T3	1		T29	2		T74	4
all_pins[11]	values[0x0]	177	1		T3	4		T5	2		T7	2
all_pins[11]	values[0x1]	33	1		T3	1		T29	2		T69	1
all_pins[11]	transitions[0x0=>0x1]	23	1		T3	1		T29	2		T74	5
all_pins[11]	transitions[0x1=>0x0]	39	1		T3	2		T27	1		T29	1
all_pins[12]	values[0x0]	161	1		T3	3		T5	2		T7	2
all_pins[12]	values[0x1]	49	1		T3	2		T27	1		T29	1
all_pins[12]	transitions[0x0=>0x1]	31	1		T27	1		T29	1		T72	3
all_pins[12]	transitions[0x1=>0x0]	21	1		T27	2		T29	2		T28	1
all_pins[13]	values[0x0]	171	1		T3	3		T5	2		T7	2
all_pins[13]	values[0x1]	39	1		T3	2		T27	2		T29	2
all_pins[13]	transitions[0x0=>0x1]	29	1		T3	2		T27	2		T29	2
all_pins[13]	transitions[0x1=>0x0]	17	1		T27	1		T28	1		T72	1
all_pins[14]	values[0x0]	183	1		T3	5		T5	2		T7	2
all_pins[14]	values[0x1]	27	1		T27	1		T28	2		T72	1
all_pins[14]	transitions[0x0=>0x1]	19	1		T27	1		T28	2		T72	1
all_pins[14]	transitions[0x1=>0x0]	27	1		T29	3		T30	2		T74	4
all_pins[15]	values[0x0]	175	1		T3	5		T5	2		T7	2
all_pins[15]	values[0x1]	35	1		T29	3		T30	2		T74	4
all_pins[15]	transitions[0x0=>0x1]	25	1		T30	2		T74	4		T67	1
all_pins[15]	transitions[0x1=>0x0]	31	1		T3	1		T27	1		T29	1
all_pins[16]	values[0x0]	169	1		T3	4		T5	2		T7	2
all_pins[16]	values[0x1]	41	1		T3	1		T27	1		T29	4
all_pins[16]	transitions[0x0=>0x1]	25	1		T3	1		T27	1		T29	3
all_pins[16]	transitions[0x1=>0x0]	27	1		T3	3		T30	1		T72	2