Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	146	1		T3	4		T27	4		T29	7
all_values[1]	146	1		T3	4		T27	4		T29	7
all_values[2]	146	1		T3	4		T27	4		T29	7
all_values[3]	146	1		T3	4		T27	4		T29	7
all_values[4]	146	1		T3	4		T27	4		T29	7
all_values[5]	146	1		T3	4		T27	4		T29	7
all_values[6]	146	1		T3	4		T27	4		T29	7
all_values[7]	146	1		T3	4		T27	4		T29	7
all_values[8]	146	1		T3	4		T27	4		T29	7
all_values[9]	146	1		T3	4		T27	4		T29	7
all_values[10]	146	1		T3	4		T27	4		T29	7
all_values[11]	146	1		T3	4		T27	4		T29	7
all_values[12]	146	1		T3	4		T27	4		T29	7
all_values[13]	146	1		T3	4		T27	4		T29	7
all_values[14]	146	1		T3	4		T27	4		T29	7
all_values[15]	146	1		T3	4		T27	4		T29	7
all_values[16]	146	1		T3	4		T27	4		T29	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1320	1		T3	35		T27	33		T29	63
auto[1]	1162	1		T3	33		T27	35		T29	56

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	434	1		T3	17		T27	13		T29	11
auto[1]	2048	1		T3	51		T27	55		T29	108

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1478	1		T3	46		T27	43		T29	69
auto[1]	1004	1		T3	22		T27	25		T29	50

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	9	1		T29	1		T28	1		T31	1
all_values[0]	auto[0]	auto[0]	auto[1]	31	1		T3	1		T29	1		T28	1
all_values[0]	auto[0]	auto[1]	auto[0]	14	1		T29	3		T72	3		T66	1
all_values[0]	auto[0]	auto[1]	auto[1]	31	1		T3	1		T27	2		T30	1
all_values[0]	auto[1]	auto[0]	auto[1]	34	1		T3	1		T27	2		T28	2
all_values[0]	auto[1]	auto[1]	auto[1]	27	1		T3	1		T29	2		T30	1
all_values[1]	auto[0]	auto[0]	auto[0]	14	1		T28	1		T31	2		T74	1
all_values[1]	auto[0]	auto[0]	auto[1]	33	1		T3	1		T27	2		T29	1
all_values[1]	auto[0]	auto[1]	auto[0]	7	1		T67	1		T76	1		T77	4
all_values[1]	auto[0]	auto[1]	auto[1]	33	1		T3	1		T29	4		T30	1
all_values[1]	auto[1]	auto[0]	auto[1]	28	1		T3	2		T27	2		T29	2
all_values[1]	auto[1]	auto[1]	auto[1]	31	1		T28	1		T30	2		T31	1
all_values[2]	auto[0]	auto[0]	auto[0]	19	1		T3	3		T72	5		T69	2
all_values[2]	auto[0]	auto[0]	auto[1]	31	1		T27	2		T29	3		T28	2
all_values[2]	auto[0]	auto[1]	auto[0]	15	1		T3	1		T72	2		T66	2
all_values[2]	auto[0]	auto[1]	auto[1]	25	1		T27	1		T29	1		T31	1
all_values[2]	auto[1]	auto[0]	auto[1]	30	1		T27	1		T29	1		T28	2
all_values[2]	auto[1]	auto[1]	auto[1]	26	1		T29	2		T31	1		T69	1
all_values[3]	auto[0]	auto[0]	auto[0]	15	1		T28	3		T30	1		T72	2
all_values[3]	auto[0]	auto[0]	auto[1]	30	1		T3	1		T27	2		T29	1
all_values[3]	auto[0]	auto[1]	auto[0]	9	1		T28	1		T72	2		T78	1
all_values[3]	auto[0]	auto[1]	auto[1]	32	1		T3	2		T27	1		T29	3
all_values[3]	auto[1]	auto[0]	auto[1]	32	1		T29	2		T31	1		T72	2
all_values[3]	auto[1]	auto[1]	auto[1]	28	1		T3	1		T27	1		T29	1
all_values[4]	auto[0]	auto[0]	auto[0]	13	1		T3	1		T29	1		T31	2
all_values[4]	auto[0]	auto[0]	auto[1]	37	1		T27	1		T29	1		T28	3
all_values[4]	auto[0]	auto[1]	auto[0]	10	1		T3	3		T29	1		T79	1
all_values[4]	auto[0]	auto[1]	auto[1]	33	1		T27	2		T29	2		T72	1
all_values[4]	auto[1]	auto[0]	auto[1]	28	1		T29	1		T28	1		T30	2
all_values[4]	auto[1]	auto[1]	auto[1]	25	1		T27	1		T29	1		T30	1
all_values[5]	auto[0]	auto[0]	auto[0]	15	1		T28	1		T30	1		T74	1
all_values[5]	auto[0]	auto[0]	auto[1]	27	1		T3	1		T29	2		T30	2
all_values[5]	auto[0]	auto[1]	auto[0]	13	1		T3	1		T28	3		T72	1
all_values[5]	auto[0]	auto[1]	auto[1]	36	1		T3	1		T27	2		T29	3
all_values[5]	auto[1]	auto[0]	auto[1]	28	1		T29	2		T31	1		T69	5
all_values[5]	auto[1]	auto[1]	auto[1]	27	1		T3	1		T27	2		T30	1
all_values[6]	auto[0]	auto[0]	auto[0]	12	1		T28	1		T72	2		T69	1
all_values[6]	auto[0]	auto[0]	auto[1]	32	1		T3	2		T27	1		T29	1
all_values[6]	auto[0]	auto[1]	auto[0]	12	1		T27	1		T69	1		T74	1
all_values[6]	auto[0]	auto[1]	auto[1]	24	1		T29	3		T28	1		T31	1
all_values[6]	auto[1]	auto[0]	auto[1]	39	1		T3	2		T27	1		T29	2
all_values[6]	auto[1]	auto[1]	auto[1]	27	1		T27	1		T29	1		T28	1
all_values[7]	auto[0]	auto[0]	auto[0]	12	1		T30	2		T31	1		T80	1
all_values[7]	auto[0]	auto[0]	auto[1]	23	1		T3	1		T29	1		T72	1
all_values[7]	auto[0]	auto[1]	auto[0]	10	1		T3	1		T30	2		T31	1
all_values[7]	auto[0]	auto[1]	auto[1]	43	1		T27	3		T29	2		T28	2
all_values[7]	auto[1]	auto[0]	auto[1]	35	1		T29	2		T28	2		T31	1
all_values[7]	auto[1]	auto[1]	auto[1]	23	1		T3	2		T27	1		T29	2
all_values[8]	auto[0]	auto[0]	auto[0]	17	1		T27	1		T30	1		T31	1
all_values[8]	auto[0]	auto[0]	auto[1]	31	1		T3	1		T29	3		T31	2
all_values[8]	auto[0]	auto[1]	auto[0]	15	1		T27	3		T30	3		T72	1
all_values[8]	auto[0]	auto[1]	auto[1]	37	1		T3	2		T29	1		T28	1
all_values[8]	auto[1]	auto[0]	auto[1]	27	1		T3	1		T29	2		T28	2
all_values[8]	auto[1]	auto[1]	auto[1]	19	1		T29	1		T28	1		T31	1
all_values[9]	auto[0]	auto[0]	auto[0]	15	1		T3	2		T29	2		T30	1
all_values[9]	auto[0]	auto[0]	auto[1]	28	1		T27	3		T28	1		T69	1
all_values[9]	auto[0]	auto[1]	auto[0]	5	1		T31	2		T66	1		T76	1
all_values[9]	auto[0]	auto[1]	auto[1]	32	1		T3	1		T29	2		T30	2
all_values[9]	auto[1]	auto[0]	auto[1]	35	1		T27	1		T28	3		T72	3
all_values[9]	auto[1]	auto[1]	auto[1]	31	1		T3	1		T29	3		T30	1
all_values[10]	auto[0]	auto[0]	auto[0]	6	1		T66	1		T75	1		T73	1
all_values[10]	auto[0]	auto[0]	auto[1]	30	1		T3	1		T27	1		T29	4
all_values[10]	auto[0]	auto[1]	auto[0]	9	1		T27	1		T66	2		T78	1
all_values[10]	auto[0]	auto[1]	auto[1]	34	1		T3	2		T29	1		T28	2
all_values[10]	auto[1]	auto[0]	auto[1]	39	1		T27	1		T29	2		T28	1
all_values[10]	auto[1]	auto[1]	auto[1]	28	1		T3	1		T27	1		T30	1
all_values[11]	auto[0]	auto[0]	auto[0]	20	1		T27	3		T30	4		T31	1
all_values[11]	auto[0]	auto[0]	auto[1]	24	1		T3	1		T29	2		T28	2
all_values[11]	auto[0]	auto[1]	auto[0]	15	1		T3	1		T27	1		T31	1
all_values[11]	auto[0]	auto[1]	auto[1]	25	1		T3	1		T29	1		T72	1
all_values[11]	auto[1]	auto[0]	auto[1]	31	1		T29	2		T28	2		T72	1
all_values[11]	auto[1]	auto[1]	auto[1]	31	1		T3	1		T29	2		T31	1
all_values[12]	auto[0]	auto[0]	auto[0]	18	1		T3	1		T30	1		T31	3
all_values[12]	auto[0]	auto[0]	auto[1]	35	1		T3	1		T27	1		T29	2
all_values[12]	auto[0]	auto[1]	auto[0]	5	1		T31	1		T66	2		T81	1
all_values[12]	auto[0]	auto[1]	auto[1]	29	1		T3	1		T29	1		T28	1
all_values[12]	auto[1]	auto[0]	auto[1]	27	1		T3	1		T29	3		T28	1
all_values[12]	auto[1]	auto[1]	auto[1]	32	1		T27	3		T29	1		T30	1
all_values[13]	auto[0]	auto[0]	auto[0]	14	1		T28	1		T30	1		T69	1
all_values[13]	auto[0]	auto[0]	auto[1]	36	1		T29	2		T28	2		T30	2
all_values[13]	auto[0]	auto[1]	auto[0]	10	1		T3	1		T79	1		T80	1
all_values[13]	auto[0]	auto[1]	auto[1]	25	1		T3	1		T27	1		T29	1
all_values[13]	auto[1]	auto[0]	auto[1]	39	1		T3	1		T27	2		T29	2
all_values[13]	auto[1]	auto[1]	auto[1]	22	1		T3	1		T27	1		T29	2
all_values[14]	auto[0]	auto[0]	auto[0]	16	1		T74	1		T66	1		T75	7
all_values[14]	auto[0]	auto[0]	auto[1]	28	1		T3	2		T27	1		T29	2
all_values[14]	auto[0]	auto[1]	auto[0]	10	1		T27	1		T72	2		T78	1
all_values[14]	auto[0]	auto[1]	auto[1]	36	1		T27	1		T29	1		T30	2
all_values[14]	auto[1]	auto[0]	auto[1]	33	1		T3	2		T29	3		T28	1
all_values[14]	auto[1]	auto[1]	auto[1]	23	1		T27	1		T29	1		T28	1
all_values[15]	auto[0]	auto[0]	auto[0]	20	1		T3	1		T28	4		T31	2
all_values[15]	auto[0]	auto[0]	auto[1]	31	1		T3	1		T27	1		T29	3
all_values[15]	auto[0]	auto[1]	auto[0]	11	1		T27	2		T31	2		T66	1
all_values[15]	auto[0]	auto[1]	auto[1]	27	1		T29	1		T30	1		T72	3
all_values[15]	auto[1]	auto[0]	auto[1]	35	1		T3	2		T27	1		T29	2
all_values[15]	auto[1]	auto[1]	auto[1]	22	1		T29	1		T69	1		T74	1
all_values[16]	auto[0]	auto[0]	auto[0]	18	1		T29	2		T30	1		T69	2
all_values[16]	auto[0]	auto[0]	auto[1]	29	1		T3	1		T27	1		T31	1
all_values[16]	auto[0]	auto[1]	auto[0]	11	1		T3	1		T29	1		T74	1
all_values[16]	auto[0]	auto[1]	auto[1]	26	1		T3	1		T27	1		T29	2
all_values[16]	auto[1]	auto[0]	auto[1]	31	1		T27	2		T28	2		T31	2
all_values[16]	auto[1]	auto[1]	auto[1]	31	1		T3	1		T29	2		T28	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal