Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	277	1		T5	2		T12	2		T21	5
all_values[1]	277	1		T5	2		T12	2		T21	5
all_values[2]	277	1		T5	2		T12	2		T21	5
all_values[3]	277	1		T5	2		T12	2		T21	5
all_values[4]	277	1		T5	2		T12	2		T21	5
all_values[5]	277	1		T5	2		T12	2		T21	5
all_values[6]	277	1		T5	2		T12	2		T21	5
all_values[7]	277	1		T5	2		T12	2		T21	5
all_values[8]	277	1		T5	2		T12	2		T21	5
all_values[9]	277	1		T5	2		T12	2		T21	5
all_values[10]	277	1		T5	2		T12	2		T21	5
all_values[11]	277	1		T5	2		T12	2		T21	5
all_values[12]	277	1		T5	2		T12	2		T21	5
all_values[13]	277	1		T5	2		T12	2		T21	5
all_values[14]	277	1		T5	2		T12	2		T21	5
all_values[15]	277	1		T5	2		T12	2		T21	5
all_values[16]	277	1		T5	2		T12	2		T21	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2690	1		T5	34		T12	34		T21	51
auto[1]	2019	1		T21	34		T16	47		T22	39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1308	1		T5	34		T12	34		T21	7
auto[1]	3401	1		T21	78		T16	67		T22	64

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	55	1		T5	2		T12	2		T16	1
all_values[0]	auto[0]	auto[1]	102	1		T21	3		T22	3		T24	1
all_values[0]	auto[1]	auto[0]	20	1		T16	1		T22	2		T71	2
all_values[0]	auto[1]	auto[1]	100	1		T21	2		T16	3		T24	4
all_values[1]	auto[0]	auto[0]	65	1		T5	2		T12	2		T16	1
all_values[1]	auto[0]	auto[1]	92	1		T21	4		T16	3		T22	1
all_values[1]	auto[1]	auto[0]	18	1		T16	1		T26	4		T23	1
all_values[1]	auto[1]	auto[1]	102	1		T21	1		T22	4		T24	3
all_values[2]	auto[0]	auto[0]	65	1		T5	2		T12	2		T15	2
all_values[2]	auto[0]	auto[1]	78	1		T21	4		T22	4		T25	2
all_values[2]	auto[1]	auto[0]	23	1		T26	3		T23	4		T72	1
all_values[2]	auto[1]	auto[1]	111	1		T21	1		T16	5		T22	1
all_values[3]	auto[0]	auto[0]	55	1		T5	2		T12	2		T21	1
all_values[3]	auto[0]	auto[1]	98	1		T16	1		T22	2		T26	3
all_values[3]	auto[1]	auto[0]	18	1		T21	1		T24	1		T26	1
all_values[3]	auto[1]	auto[1]	106	1		T21	3		T16	4		T22	3
all_values[4]	auto[0]	auto[0]	48	1		T5	2		T12	2		T16	1
all_values[4]	auto[0]	auto[1]	100	1		T16	1		T22	5		T26	3
all_values[4]	auto[1]	auto[0]	13	1		T71	2		T73	1		T74	1
all_values[4]	auto[1]	auto[1]	116	1		T21	5		T16	3		T24	5
all_values[5]	auto[0]	auto[0]	61	1		T5	2		T12	2		T16	1
all_values[5]	auto[0]	auto[1]	111	1		T21	3		T22	5		T24	2
all_values[5]	auto[1]	auto[0]	18	1		T21	1		T16	4		T23	1
all_values[5]	auto[1]	auto[1]	87	1		T21	1		T24	3		T25	2
all_values[6]	auto[0]	auto[0]	66	1		T5	2		T12	2		T21	2
all_values[6]	auto[0]	auto[1]	100	1		T21	3		T16	5		T24	3
all_values[6]	auto[1]	auto[0]	26	1		T22	1		T25	4		T73	1
all_values[6]	auto[1]	auto[1]	85	1		T22	3		T24	2		T26	3
all_values[7]	auto[0]	auto[0]	59	1		T5	2		T12	2		T16	4
all_values[7]	auto[0]	auto[1]	100	1		T21	3		T22	1		T24	4
all_values[7]	auto[1]	auto[0]	21	1		T21	1		T16	1		T22	1
all_values[7]	auto[1]	auto[1]	97	1		T21	1		T22	3		T24	1
all_values[8]	auto[0]	auto[0]	57	1		T5	2		T12	2		T15	2
all_values[8]	auto[0]	auto[1]	102	1		T16	4		T24	3		T26	1
all_values[8]	auto[1]	auto[0]	17	1		T22	3		T23	1		T72	1
all_values[8]	auto[1]	auto[1]	101	1		T21	5		T16	1		T24	2
all_values[9]	auto[0]	auto[0]	50	1		T5	2		T12	2		T15	2
all_values[9]	auto[0]	auto[1]	100	1		T21	4		T16	1		T22	3
all_values[9]	auto[1]	auto[0]	12	1		T24	1		T75	1		T76	1
all_values[9]	auto[1]	auto[1]	115	1		T21	1		T16	4		T22	1
all_values[10]	auto[0]	auto[0]	61	1		T5	2		T12	2		T15	2
all_values[10]	auto[0]	auto[1]	96	1		T21	4		T16	2		T24	3
all_values[10]	auto[1]	auto[0]	15	1		T22	1		T23	1		T71	1
all_values[10]	auto[1]	auto[1]	105	1		T21	1		T16	3		T24	2
all_values[11]	auto[0]	auto[0]	59	1		T5	2		T12	2		T15	2
all_values[11]	auto[0]	auto[1]	106	1		T21	1		T16	3		T24	1
all_values[11]	auto[1]	auto[0]	28	1		T24	1		T23	3		T73	1
all_values[11]	auto[1]	auto[1]	84	1		T21	4		T16	2		T22	5
all_values[12]	auto[0]	auto[0]	61	1		T5	2		T12	2		T15	2
all_values[12]	auto[0]	auto[1]	89	1		T21	5		T16	3		T22	4
all_values[12]	auto[1]	auto[0]	19	1		T25	1		T77	1		T72	1
all_values[12]	auto[1]	auto[1]	108	1		T16	2		T22	1		T24	2
all_values[13]	auto[0]	auto[0]	63	1		T5	2		T12	2		T15	2
all_values[13]	auto[0]	auto[1]	108	1		T21	4		T16	1		T22	1
all_values[13]	auto[1]	auto[0]	24	1		T21	1		T16	1		T77	2
all_values[13]	auto[1]	auto[1]	82	1		T16	3		T22	4		T24	5
all_values[14]	auto[0]	auto[0]	58	1		T5	2		T12	2		T15	2
all_values[14]	auto[0]	auto[1]	97	1		T21	1		T16	4		T22	4
all_values[14]	auto[1]	auto[0]	15	1		T72	3		T78	4		T79	1
all_values[14]	auto[1]	auto[1]	107	1		T21	4		T16	1		T22	1
all_values[15]	auto[0]	auto[0]	60	1		T5	2		T12	2		T15	2
all_values[15]	auto[0]	auto[1]	94	1		T21	4		T16	1		T24	3
all_values[15]	auto[1]	auto[0]	14	1		T16	1		T22	3		T23	1
all_values[15]	auto[1]	auto[1]	109	1		T21	1		T16	3		T26	4
all_values[16]	auto[0]	auto[0]	52	1		T5	2		T12	2		T15	2
all_values[16]	auto[0]	auto[1]	122	1		T21	5		T16	1		T22	3
all_values[16]	auto[1]	auto[0]	12	1		T16	1		T26	1		T23	1
all_values[16]	auto[1]	auto[1]	91	1		T16	3		T22	2		T24	3