Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.97	89.84	75.33	95.05	3.12	87.16	92.01	96.28

Total tests in report: 148

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
53.14	53.14	66.79	66.79	59.16	59.16	79.89	79.89	0.00	0.00	72.41	72.41	66.60	66.60	27.14	27.14	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1665531174
64.79	11.65	89.02	22.23	71.16	12.00	88.39	8.49	3.12	3.12	86.85	14.44	87.50	20.90	27.51	0.37	/workspace/coverage/default/1.usbdev_sec_cm.2156251512
70.75	5.96	89.75	0.73	72.75	1.59	90.97	2.58	3.12	0.00	86.85	0.00	87.70	0.20	64.13	36.62	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.3100085740
72.86	2.10	89.80	0.04	73.95	1.20	93.55	2.58	3.12	0.00	86.90	0.04	88.52	0.82	74.16	10.04	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2649497055
74.36	1.50	89.80	0.00	73.95	0.00	94.19	0.65	3.12	0.00	86.90	0.00	88.52	0.00	84.01	9.85	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2542041031
75.04	0.68	89.82	0.02	74.05	0.10	94.19	0.00	3.12	0.00	86.94	0.04	90.16	1.64	86.99	2.97	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1866672733
75.60	0.56	89.82	0.00	74.05	0.00	94.19	0.00	3.12	0.00	86.94	0.00	90.16	0.00	90.89	3.90	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3920635277
75.97	0.37	89.84	0.02	75.15	1.10	94.41	0.22	3.12	0.00	87.16	0.22	91.19	1.02	90.89	0.00	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1959694937
76.26	0.29	90.22	0.38	75.15	0.00	94.41	0.00	3.12	0.00	87.16	0.00	91.19	0.00	92.57	1.67	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.2717964417
76.44	0.18	90.22	0.00	75.26	0.10	94.41	0.00	3.12	0.00	87.16	0.00	92.01	0.82	92.94	0.37	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2040028105
76.60	0.16	90.22	0.00	75.26	0.00	94.41	0.00	3.12	0.00	87.16	0.00	92.01	0.00	94.05	1.12	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.4254794438
76.74	0.13	90.22	0.00	75.26	0.00	94.41	0.00	3.12	0.00	87.16	0.00	92.01	0.00	94.98	0.93	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.298600879
76.82	0.08	90.22	0.00	75.26	0.00	94.41	0.00	3.12	0.00	87.16	0.00	92.01	0.00	95.54	0.56	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.1735766686
76.88	0.06	90.22	0.00	75.26	0.00	94.84	0.43	3.12	0.00	87.16	0.00	92.01	0.00	95.54	0.00	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1952652946
76.93	0.06	90.22	0.00	75.28	0.03	94.84	0.00	3.12	0.00	87.16	0.00	92.01	0.00	95.91	0.37	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2575917632
76.96	0.03	90.22	0.00	75.28	0.00	95.05	0.22	3.12	0.00	87.16	0.00	92.01	0.00	95.91	0.00	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2864376563
76.99	0.03	90.22	0.00	75.28	0.00	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.10	0.19	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2703185689
77.02	0.03	90.22	0.00	75.28	0.00	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.28	0.19	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2925852188
77.02	0.01	90.22	0.00	75.31	0.03	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.28	0.00	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3598145854
77.02	0.01	90.22	0.00	75.33	0.03	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.28	0.00	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2168777060

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3580531077
/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2713828214
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2753608756
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1926994576
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.3660403636
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1398391205
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2229622655
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1601951010
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.135393783
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1993113119
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3640017302
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3670083244
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1532770905
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.962961082
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3868574326
/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1463151259
/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2158119481
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.511174407
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3533704739
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.409113365
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3009975575
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1798910807
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2892988906
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1566853034
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2234545032
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3726057096
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3047393271
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.3360270519
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.432461994
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2745042633
/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.732452445
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2411533930
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1848161737
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3639712966
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3797119698
/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3322287501
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2301297280
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1658858538
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2412013513
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1665247355
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2207217884
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4026011292
/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3853974808
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1696633285
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.735589608
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1194731092
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1561212357
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1969800920
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1485278770
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1074701550
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3125960700
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.985915384
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.573979780
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2013692845
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.4124372503
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4094853412
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.642625226
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1259350718
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1234112697
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2776195861
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2479355429
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.50912025
/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2160308199
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1048691320
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3163895827
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.1167825016
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3655895321
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2702777876
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2025105992
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.70965402
/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2094092403
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.1454239619
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2131804981
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.1605572608
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.591413675
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.342577880
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1585219697
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.4275885105
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3118700035
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3138672642
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3507198865
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1357934073
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3886826539
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.131342717
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3033782038
/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3664871117
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3044721478
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3591306002
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.1533010270
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.220195281
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3545511480
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2092422517
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1976034035
/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3389969501
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1854983765
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3623966318
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3235973444
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2105020641
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1380009776
/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.240766912
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.1201483305
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.1864321640
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.3291017890
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.485510499
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2017628791
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.202411211
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1202236660
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3386007440
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2774503335
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3683075061
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.958641276
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3452350974
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2938448861
/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1151518943
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1799310210
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2706869823
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3001712329
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4208123920
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2204587700
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.616728131
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4134844292
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3387421348
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1028885806
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1080388319
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.290927136
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1440661835
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.132812742
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1294366385

Total test records in report: 148

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.usbdev_sec_cm.2156251512	Jan 10 01:01:37 PM PST 24	Jan 10 01:03:13 PM PST 24	223446755 ps
T2	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1665531174	Jan 10 01:09:32 PM PST 24	Jan 10 01:10:38 PM PST 24	49269144 ps
T3	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3507198865	Jan 10 01:09:41 PM PST 24	Jan 10 01:10:48 PM PST 24	54758435 ps
T4	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3726057096	Jan 10 01:09:49 PM PST 24	Jan 10 01:10:56 PM PST 24	29530748 ps
T5	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2649497055	Jan 10 01:09:38 PM PST 24	Jan 10 01:10:46 PM PST 24	179354252 ps
T6	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2207217884	Jan 10 01:09:53 PM PST 24	Jan 10 01:11:00 PM PST 24	43323952 ps
T7	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3386007440	Jan 10 01:09:49 PM PST 24	Jan 10 01:10:56 PM PST 24	62869592 ps
T8	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1080388319	Jan 10 01:09:38 PM PST 24	Jan 10 01:10:44 PM PST 24	27768628 ps
T9	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1798910807	Jan 10 01:09:36 PM PST 24	Jan 10 01:10:42 PM PST 24	49841469 ps
T10	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2864376563	Jan 10 01:09:39 PM PST 24	Jan 10 01:10:45 PM PST 24	31312649 ps
T11	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1696633285	Jan 10 01:10:10 PM PST 24	Jan 10 01:11:23 PM PST 24	43080348 ps
T12	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.70965402	Jan 10 01:09:44 PM PST 24	Jan 10 01:10:53 PM PST 24	286128615 ps
T27	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4094853412	Jan 10 01:10:00 PM PST 24	Jan 10 01:11:10 PM PST 24	61698068 ps
T28	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2229622655	Jan 10 01:09:35 PM PST 24	Jan 10 01:10:41 PM PST 24	37436112 ps
T29	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3452350974	Jan 10 01:10:01 PM PST 24	Jan 10 01:11:10 PM PST 24	107658112 ps
T13	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.962961082	Jan 10 01:09:25 PM PST 24	Jan 10 01:10:33 PM PST 24	154668704 ps
T62	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2575917632	Jan 10 01:09:59 PM PST 24	Jan 10 01:11:08 PM PST 24	150792760 ps
T19	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1959694937	Jan 10 01:09:36 PM PST 24	Jan 10 01:10:42 PM PST 24	173425424 ps
T49	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2040028105	Jan 10 01:10:15 PM PST 24	Jan 10 01:11:29 PM PST 24	31005276 ps
T21	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.3100085740	Jan 10 01:09:46 PM PST 24	Jan 10 01:10:53 PM PST 24	34039583 ps
T14	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2411533930	Jan 10 01:09:36 PM PST 24	Jan 10 01:10:42 PM PST 24	39124875 ps
T16	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.2717964417	Jan 10 01:09:34 PM PST 24	Jan 10 01:10:39 PM PST 24	34334844 ps
T15	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3683075061	Jan 10 01:09:40 PM PST 24	Jan 10 01:10:47 PM PST 24	92297926 ps
T37	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1048691320	Jan 10 01:09:34 PM PST 24	Jan 10 01:10:41 PM PST 24	52295420 ps
T38	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1993113119	Jan 10 01:09:44 PM PST 24	Jan 10 01:10:55 PM PST 24	193219358 ps
T39	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2013692845	Jan 10 01:10:03 PM PST 24	Jan 10 01:11:12 PM PST 24	63551124 ps
T22	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.3291017890	Jan 10 01:10:06 PM PST 24	Jan 10 01:11:17 PM PST 24	26124178 ps
T40	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2301297280	Jan 10 01:10:00 PM PST 24	Jan 10 01:11:09 PM PST 24	74820111 ps
T41	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3868574326	Jan 10 01:09:25 PM PST 24	Jan 10 01:10:31 PM PST 24	43469781 ps
T42	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.511174407	Jan 10 01:09:39 PM PST 24	Jan 10 01:10:46 PM PST 24	25083480 ps
T50	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2774503335	Jan 10 01:09:47 PM PST 24	Jan 10 01:10:55 PM PST 24	58794517 ps
T51	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3670083244	Jan 10 01:09:26 PM PST 24	Jan 10 01:10:34 PM PST 24	77416085 ps
T52	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3580531077	Jan 10 01:09:25 PM PST 24	Jan 10 01:10:33 PM PST 24	339578470 ps
T43	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1294366385	Jan 10 01:09:46 PM PST 24	Jan 10 01:10:55 PM PST 24	445241023 ps
T24	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.202411211	Jan 10 01:09:57 PM PST 24	Jan 10 01:11:04 PM PST 24	23452414 ps
T26	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.1605572608	Jan 10 01:10:06 PM PST 24	Jan 10 01:11:17 PM PST 24	26854123 ps
T53	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3886826539	Jan 10 01:09:33 PM PST 24	Jan 10 01:10:40 PM PST 24	45580446 ps
T55	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1976034035	Jan 10 01:09:32 PM PST 24	Jan 10 01:10:41 PM PST 24	116917635 ps
T45	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.298600879	Jan 10 01:09:32 PM PST 24	Jan 10 01:10:42 PM PST 24	480878730 ps
T54	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4134844292	Jan 10 01:09:33 PM PST 24	Jan 10 01:10:39 PM PST 24	43007655 ps
T56	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1926994576	Jan 10 01:09:45 PM PST 24	Jan 10 01:10:52 PM PST 24	69583462 ps
T86	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.958641276	Jan 10 01:09:32 PM PST 24	Jan 10 01:10:38 PM PST 24	31617315 ps
T30	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3598145854	Jan 10 01:09:49 PM PST 24	Jan 10 01:10:57 PM PST 24	74137154 ps
T23	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1566853034	Jan 10 01:09:44 PM PST 24	Jan 10 01:10:52 PM PST 24	61746896 ps
T85	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2753608756	Jan 10 01:09:28 PM PST 24	Jan 10 01:10:35 PM PST 24	119728286 ps
T87	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3235973444	Jan 10 01:09:29 PM PST 24	Jan 10 01:10:36 PM PST 24	273303336 ps
T65	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1028885806	Jan 10 01:10:09 PM PST 24	Jan 10 01:11:22 PM PST 24	34223304 ps
T88	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3001712329	Jan 10 01:09:32 PM PST 24	Jan 10 01:10:38 PM PST 24	130407639 ps
T57	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1234112697	Jan 10 01:10:08 PM PST 24	Jan 10 01:11:20 PM PST 24	73117762 ps
T31	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1866672733	Jan 10 01:09:58 PM PST 24	Jan 10 01:11:09 PM PST 24	346242924 ps
T89	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2479355429	Jan 10 01:09:57 PM PST 24	Jan 10 01:11:05 PM PST 24	128153270 ps
T90	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1799310210	Jan 10 01:09:47 PM PST 24	Jan 10 01:10:55 PM PST 24	45674665 ps
T58	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3655895321	Jan 10 01:09:32 PM PST 24	Jan 10 01:10:39 PM PST 24	88202611 ps
T32	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2745042633	Jan 10 01:09:35 PM PST 24	Jan 10 01:10:41 PM PST 24	156100496 ps
T91	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3033782038	Jan 10 01:09:38 PM PST 24	Jan 10 01:10:44 PM PST 24	33577267 ps
T59	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3138672642	Jan 10 01:09:38 PM PST 24	Jan 10 01:10:53 PM PST 24	479408270 ps
T92	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2702777876	Jan 10 01:09:38 PM PST 24	Jan 10 01:10:45 PM PST 24	86551915 ps
T25	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3322287501	Jan 10 01:09:59 PM PST 24	Jan 10 01:11:07 PM PST 24	22827634 ps
T44	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3853974808	Jan 10 01:10:07 PM PST 24	Jan 10 01:11:20 PM PST 24	285571567 ps
T71	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.591413675	Jan 10 01:09:46 PM PST 24	Jan 10 01:10:53 PM PST 24	28042488 ps
T77	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.1167825016	Jan 10 01:09:28 PM PST 24	Jan 10 01:10:34 PM PST 24	25088718 ps
T33	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.732452445	Jan 10 01:09:35 PM PST 24	Jan 10 01:10:44 PM PST 24	256530894 ps
T93	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1969800920	Jan 10 01:09:45 PM PST 24	Jan 10 01:10:53 PM PST 24	82600504 ps
T73	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2542041031	Jan 10 01:10:09 PM PST 24	Jan 10 01:11:21 PM PST 24	31948169 ps
T94	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3640017302	Jan 10 01:09:22 PM PST 24	Jan 10 01:10:28 PM PST 24	41554158 ps
T95	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1665247355	Jan 10 01:09:46 PM PST 24	Jan 10 01:10:53 PM PST 24	62835993 ps
T96	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1194731092	Jan 10 01:10:14 PM PST 24	Jan 10 01:11:28 PM PST 24	74831067 ps
T97	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3047393271	Jan 10 01:09:45 PM PST 24	Jan 10 01:10:52 PM PST 24	30673445 ps
T20	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2713828214	Jan 10 01:09:24 PM PST 24	Jan 10 01:10:29 PM PST 24	23999138 ps
T98	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.735589608	Jan 10 01:09:52 PM PST 24	Jan 10 01:10:58 PM PST 24	46583772 ps
T70	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2094092403	Jan 10 01:09:35 PM PST 24	Jan 10 01:10:43 PM PST 24	294830930 ps
T34	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2925852188	Jan 10 01:10:09 PM PST 24	Jan 10 01:11:25 PM PST 24	276876078 ps
T17	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3389969501	Jan 10 01:09:39 PM PST 24	Jan 10 01:10:46 PM PST 24	39236724 ps
T60	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1848161737	Jan 10 01:09:35 PM PST 24	Jan 10 01:10:40 PM PST 24	26138057 ps
T99	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.131342717	Jan 10 01:09:44 PM PST 24	Jan 10 01:10:54 PM PST 24	174037650 ps
T100	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3009975575	Jan 10 01:09:37 PM PST 24	Jan 10 01:10:43 PM PST 24	120205866 ps
T72	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.4254794438	Jan 10 01:10:10 PM PST 24	Jan 10 01:11:22 PM PST 24	18437335 ps
T74	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.409113365	Jan 10 01:09:57 PM PST 24	Jan 10 01:11:04 PM PST 24	29329659 ps
T35	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3664871117	Jan 10 01:09:54 PM PST 24	Jan 10 01:11:02 PM PST 24	461202925 ps
T46	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2158119481	Jan 10 01:09:45 PM PST 24	Jan 10 01:10:55 PM PST 24	313990124 ps
T75	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1074701550	Jan 10 01:10:18 PM PST 24	Jan 10 01:11:33 PM PST 24	23693228 ps
T61	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1532770905	Jan 10 01:09:36 PM PST 24	Jan 10 01:10:43 PM PST 24	103906974 ps
T101	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3118700035	Jan 10 01:09:36 PM PST 24	Jan 10 01:10:43 PM PST 24	164203679 ps
T48	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1151518943	Jan 10 01:10:01 PM PST 24	Jan 10 01:11:12 PM PST 24	277857149 ps
T36	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1561212357	Jan 10 01:09:54 PM PST 24	Jan 10 01:11:03 PM PST 24	98651496 ps
T102	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1259350718	Jan 10 01:09:50 PM PST 24	Jan 10 01:10:57 PM PST 24	42545446 ps
T103	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3797119698	Jan 10 01:09:47 PM PST 24	Jan 10 01:10:55 PM PST 24	59952352 ps
T66	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2892988906	Jan 10 01:09:52 PM PST 24	Jan 10 01:11:04 PM PST 24	80690203 ps
T78	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3591306002	Jan 10 01:09:54 PM PST 24	Jan 10 01:11:00 PM PST 24	23676769 ps
T79	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.3660403636	Jan 10 01:09:30 PM PST 24	Jan 10 01:10:35 PM PST 24	26234783 ps
T67	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2204587700	Jan 10 01:10:00 PM PST 24	Jan 10 01:11:09 PM PST 24	46956435 ps
T68	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.432461994	Jan 10 01:09:33 PM PST 24	Jan 10 01:10:39 PM PST 24	92115101 ps
T69	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2706869823	Jan 10 01:09:33 PM PST 24	Jan 10 01:10:39 PM PST 24	68472270 ps
T47	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.50912025	Jan 10 01:09:44 PM PST 24	Jan 10 01:10:52 PM PST 24	54043820 ps
T104	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.573979780	Jan 10 01:09:52 PM PST 24	Jan 10 01:10:59 PM PST 24	39385722 ps
T105	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2160308199	Jan 10 01:09:53 PM PST 24	Jan 10 01:11:02 PM PST 24	302407317 ps
T81	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.1201483305	Jan 10 01:10:17 PM PST 24	Jan 10 01:11:32 PM PST 24	31016079 ps
T80	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3044721478	Jan 10 01:10:06 PM PST 24	Jan 10 01:11:19 PM PST 24	51590060 ps
T64	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2938448861	Jan 10 01:09:42 PM PST 24	Jan 10 01:10:55 PM PST 24	274075946 ps
T106	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1440661835	Jan 10 01:09:32 PM PST 24	Jan 10 01:10:37 PM PST 24	76800312 ps
T107	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3125960700	Jan 10 01:10:13 PM PST 24	Jan 10 01:11:32 PM PST 24	70797207 ps
T76	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3920635277	Jan 10 01:09:33 PM PST 24	Jan 10 01:10:39 PM PST 24	33405090 ps
T108	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.4275885105	Jan 10 01:09:59 PM PST 24	Jan 10 01:11:07 PM PST 24	57128738 ps
T109	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1463151259	Jan 10 01:09:54 PM PST 24	Jan 10 01:11:01 PM PST 24	47492656 ps
T83	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.1735766686	Jan 10 01:09:36 PM PST 24	Jan 10 01:10:42 PM PST 24	45843253 ps
T110	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.1454239619	Jan 10 01:10:11 PM PST 24	Jan 10 01:11:23 PM PST 24	22113255 ps
T111	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1585219697	Jan 10 01:09:58 PM PST 24	Jan 10 01:11:05 PM PST 24	42971129 ps
T82	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2131804981	Jan 10 01:10:09 PM PST 24	Jan 10 01:11:22 PM PST 24	45524959 ps
T112	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.985915384	Jan 10 01:10:16 PM PST 24	Jan 10 01:11:30 PM PST 24	51939357 ps
T113	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1485278770	Jan 10 01:10:01 PM PST 24	Jan 10 01:11:10 PM PST 24	31314082 ps
T114	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1357934073	Jan 10 01:09:54 PM PST 24	Jan 10 01:11:06 PM PST 24	22328310 ps
T115	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.220195281	Jan 10 01:10:15 PM PST 24	Jan 10 01:11:28 PM PST 24	24042695 ps
T116	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2017628791	Jan 10 01:09:52 PM PST 24	Jan 10 01:10:59 PM PST 24	61073904 ps
T117	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.4124372503	Jan 10 01:09:57 PM PST 24	Jan 10 01:11:05 PM PST 24	27722952 ps
T118	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1658858538	Jan 10 01:10:00 PM PST 24	Jan 10 01:11:08 PM PST 24	49852132 ps
T119	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4026011292	Jan 10 01:10:06 PM PST 24	Jan 10 01:11:21 PM PST 24	171568734 ps
T120	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3163895827	Jan 10 01:09:35 PM PST 24	Jan 10 01:10:40 PM PST 24	36372167 ps
T121	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3387421348	Jan 10 01:09:48 PM PST 24	Jan 10 01:10:56 PM PST 24	155352166 ps
T84	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.485510499	Jan 10 01:10:17 PM PST 24	Jan 10 01:11:36 PM PST 24	31756144 ps
T122	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3639712966	Jan 10 01:09:32 PM PST 24	Jan 10 01:10:39 PM PST 24	134494905 ps
T123	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.1864321640	Jan 10 01:10:08 PM PST 24	Jan 10 01:11:20 PM PST 24	23126909 ps
T124	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.616728131	Jan 10 01:09:39 PM PST 24	Jan 10 01:10:46 PM PST 24	50913536 ps
T125	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2776195861	Jan 10 01:10:08 PM PST 24	Jan 10 01:11:20 PM PST 24	24318224 ps
T126	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.132812742	Jan 10 01:09:33 PM PST 24	Jan 10 01:10:41 PM PST 24	335114586 ps
T127	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2092422517	Jan 10 01:10:11 PM PST 24	Jan 10 01:11:24 PM PST 24	20625605 ps
T128	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.3360270519	Jan 10 01:09:50 PM PST 24	Jan 10 01:10:56 PM PST 24	31699887 ps
T129	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2234545032	Jan 10 01:09:37 PM PST 24	Jan 10 01:10:45 PM PST 24	270196898 ps
T18	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1952652946	Jan 10 01:09:31 PM PST 24	Jan 10 01:10:36 PM PST 24	53228879 ps
T130	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1398391205	Jan 10 01:09:22 PM PST 24	Jan 10 01:10:29 PM PST 24	103488093 ps
T131	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1601951010	Jan 10 01:09:44 PM PST 24	Jan 10 01:10:53 PM PST 24	140432342 ps
T132	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3533704739	Jan 10 01:09:33 PM PST 24	Jan 10 01:10:39 PM PST 24	27693883 ps
T133	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2105020641	Jan 10 01:09:42 PM PST 24	Jan 10 01:10:49 PM PST 24	71411596 ps
T134	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.642625226	Jan 10 01:10:22 PM PST 24	Jan 10 01:11:40 PM PST 24	153255904 ps
T135	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.342577880	Jan 10 01:09:52 PM PST 24	Jan 10 01:10:58 PM PST 24	43682389 ps
T136	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.135393783	Jan 10 01:09:27 PM PST 24	Jan 10 01:10:33 PM PST 24	73941797 ps
T137	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1380009776	Jan 10 01:09:38 PM PST 24	Jan 10 01:10:48 PM PST 24	339546405 ps
T138	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2412013513	Jan 10 01:09:50 PM PST 24	Jan 10 01:10:57 PM PST 24	77757714 ps
T139	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.290927136	Jan 10 01:09:36 PM PST 24	Jan 10 01:10:41 PM PST 24	27701649 ps
T140	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1202236660	Jan 10 01:09:46 PM PST 24	Jan 10 01:10:54 PM PST 24	31386944 ps
T141	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.240766912	Jan 10 01:09:42 PM PST 24	Jan 10 01:10:51 PM PST 24	130785235 ps
T142	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2703185689	Jan 10 01:09:34 PM PST 24	Jan 10 01:10:39 PM PST 24	29564707 ps
T143	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.1533010270	Jan 10 01:09:58 PM PST 24	Jan 10 01:11:06 PM PST 24	30023674 ps
T144	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4208123920	Jan 10 01:09:58 PM PST 24	Jan 10 01:11:07 PM PST 24	72160110 ps
T63	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2168777060	Jan 10 01:09:59 PM PST 24	Jan 10 01:11:10 PM PST 24	307548234 ps
T145	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3623966318	Jan 10 01:09:30 PM PST 24	Jan 10 01:10:37 PM PST 24	170326638 ps
T146	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1854983765	Jan 10 01:09:36 PM PST 24	Jan 10 01:10:43 PM PST 24	54793967 ps
T147	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2025105992	Jan 10 01:09:50 PM PST 24	Jan 10 01:10:57 PM PST 24	90321098 ps
T148	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3545511480	Jan 10 01:10:14 PM PST 24	Jan 10 01:11:27 PM PST 24	32613624 ps

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1665531174
Short name	T2
Test name
Test status
Simulation time	49269144 ps
CPU time	2 seconds
Started	Jan 10 01:09:32 PM PST 24
Finished	Jan 10 01:10:38 PM PST 24
Peak memory	213392 kb
Host	smart-7fee4eb5-3551-4df7-a831-c1ff5390160f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665531174 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.1665531174
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/1.usbdev_sec_cm.2156251512
Short name	T1
Test name
Test status
Simulation time	223446755 ps
CPU time	1.05 seconds
Started	Jan 10 01:01:37 PM PST 24
Finished	Jan 10 01:03:13 PM PST 24
Peak memory	221772 kb
Host	smart-fbb37b9d-eba0-4617-9bc2-6dc53c01ace6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2156251512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2156251512
Directory	/workspace/1.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.3100085740
Short name	T21
Test name
Test status
Simulation time	34039583 ps
CPU time	0.65 seconds
Started	Jan 10 01:09:46 PM PST 24
Finished	Jan 10 01:10:53 PM PST 24
Peak memory	201368 kb
Host	smart-eecfa6b6-0cca-44fe-865a-d8f173455657
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3100085740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3100085740
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2649497055
Short name	T5
Test name
Test status
Simulation time	179354252 ps
CPU time	2.23 seconds
Started	Jan 10 01:09:38 PM PST 24
Finished	Jan 10 01:10:46 PM PST 24
Peak memory	202360 kb
Host	smart-0da2795d-bb98-43f9-81c2-1bbe4fc7235e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2649497055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2649497055
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2542041031
Short name	T73
Test name
Test status
Simulation time	31948169 ps
CPU time	0.62 seconds
Started	Jan 10 01:10:09 PM PST 24
Finished	Jan 10 01:11:21 PM PST 24
Peak memory	201340 kb
Host	smart-b875774c-e3dc-4e1c-9649-bd1129b69331
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2542041031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2542041031
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1866672733
Short name	T31
Test name
Test status
Simulation time	346242924 ps
CPU time	2.89 seconds
Started	Jan 10 01:09:58 PM PST 24
Finished	Jan 10 01:11:09 PM PST 24
Peak memory	202272 kb
Host	smart-a9bd57dc-90f9-4b97-a2c8-a680fd2f8507
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1866672733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1866672733
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3920635277
Short name	T76
Test name
Test status
Simulation time	33405090 ps
CPU time	0.62 seconds
Started	Jan 10 01:09:33 PM PST 24
Finished	Jan 10 01:10:39 PM PST 24
Peak memory	201420 kb
Host	smart-35797ee2-d7cb-4ccc-994d-1108b660d9f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3920635277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3920635277
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1959694937
Short name	T19
Test name
Test status
Simulation time	173425424 ps
CPU time	0.8 seconds
Started	Jan 10 01:09:36 PM PST 24
Finished	Jan 10 01:10:42 PM PST 24
Peak memory	201948 kb
Host	smart-ea8f8464-bee8-4de8-bfce-f09097a1eef3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959694937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1959694937
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.2717964417
Short name	T16
Test name
Test status
Simulation time	34334844 ps
CPU time	0.63 seconds
Started	Jan 10 01:09:34 PM PST 24
Finished	Jan 10 01:10:39 PM PST 24
Peak memory	201444 kb
Host	smart-06bf6947-f81d-4aec-87cb-31424e8ec9ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2717964417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2717964417
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2040028105
Short name	T49
Test name
Test status
Simulation time	31005276 ps
CPU time	0.95 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:29 PM PST 24
Peak memory	202324 kb
Host	smart-8bafb49c-33fd-454d-b361-b54ce94744e3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040028105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2040028105
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.4254794438
Short name	T72
Test name
Test status
Simulation time	18437335 ps
CPU time	0.61 seconds
Started	Jan 10 01:10:10 PM PST 24
Finished	Jan 10 01:11:22 PM PST 24
Peak memory	201136 kb
Host	smart-47453a5e-ba29-4470-9507-2a8af002537a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4254794438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4254794438
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.298600879
Short name	T45
Test name
Test status
Simulation time	480878730 ps
CPU time	4.89 seconds
Started	Jan 10 01:09:32 PM PST 24
Finished	Jan 10 01:10:42 PM PST 24
Peak memory	202380 kb
Host	smart-0b471d2f-6795-434a-bbd0-13700a0b2afc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=298600879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.298600879
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.1735766686
Short name	T83
Test name
Test status
Simulation time	45843253 ps
CPU time	0.64 seconds
Started	Jan 10 01:09:36 PM PST 24
Finished	Jan 10 01:10:42 PM PST 24
Peak memory	201400 kb
Host	smart-5dea6c18-7711-47df-94a9-9804ed169069
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1735766686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1735766686
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1952652946
Short name	T18
Test name
Test status
Simulation time	53228879 ps
CPU time	0.76 seconds
Started	Jan 10 01:09:31 PM PST 24
Finished	Jan 10 01:10:36 PM PST 24
Peak memory	202004 kb
Host	smart-ac2098c8-3e3d-4554-9bd9-fd14d60d1e46
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952652946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1952652946
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2575917632
Short name	T62
Test name
Test status
Simulation time	150792760 ps
CPU time	1.5 seconds
Started	Jan 10 01:09:59 PM PST 24
Finished	Jan 10 01:11:08 PM PST 24
Peak memory	202320 kb
Host	smart-cc56f6ea-ee5e-4e7e-a18d-39190acac8b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575917632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_ csr_outstanding.2575917632
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2864376563
Short name	T10
Test name
Test status
Simulation time	31312649 ps
CPU time	0.71 seconds
Started	Jan 10 01:09:39 PM PST 24
Finished	Jan 10 01:10:45 PM PST 24
Peak memory	202152 kb
Host	smart-ab00f541-f24c-42b1-ab6f-bebd0e5ce200
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864376563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2864376563
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2703185689
Short name	T142
Test name
Test status
Simulation time	29564707 ps
CPU time	0.65 seconds
Started	Jan 10 01:09:34 PM PST 24
Finished	Jan 10 01:10:39 PM PST 24
Peak memory	201332 kb
Host	smart-769b5c20-c576-4d28-a041-164587ca66e7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2703185689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2703185689
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2925852188
Short name	T34
Test name
Test status
Simulation time	276876078 ps
CPU time	4.02 seconds
Started	Jan 10 01:10:09 PM PST 24
Finished	Jan 10 01:11:25 PM PST 24
Peak memory	202296 kb
Host	smart-efbe6d13-8385-4f8c-af6c-4c7b5fe045a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2925852188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2925852188
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3598145854
Short name	T30
Test name
Test status
Simulation time	74137154 ps
CPU time	2.18 seconds
Started	Jan 10 01:09:49 PM PST 24
Finished	Jan 10 01:10:57 PM PST 24
Peak memory	202220 kb
Host	smart-88caa34f-8d58-4f9e-a4ec-4b21fb354800
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3598145854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3598145854
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2168777060
Short name	T63
Test name
Test status
Simulation time	307548234 ps
CPU time	3.37 seconds
Started	Jan 10 01:09:59 PM PST 24
Finished	Jan 10 01:11:10 PM PST 24
Peak memory	202296 kb
Host	smart-3349b7a6-2ee9-4ff7-8d56-6f2fde131c08
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168777060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2168777060
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3580531077
Short name	T52
Test name
Test status
Simulation time	339578470 ps
CPU time	3.38 seconds
Started	Jan 10 01:09:25 PM PST 24
Finished	Jan 10 01:10:33 PM PST 24
Peak memory	202324 kb
Host	smart-a7ca8383-201e-404d-a48e-ba654117a635
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580531077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3580531077
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2713828214
Short name	T20
Test name
Test status
Simulation time	23999138 ps
CPU time	0.69 seconds
Started	Jan 10 01:09:24 PM PST 24
Finished	Jan 10 01:10:29 PM PST 24
Peak memory	202084 kb
Host	smart-994bc8ff-0a87-42f9-80a6-017225f71728
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713828214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2713828214
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2753608756
Short name	T85
Test name
Test status
Simulation time	119728286 ps
CPU time	1.03 seconds
Started	Jan 10 01:09:28 PM PST 24
Finished	Jan 10 01:10:35 PM PST 24
Peak memory	202284 kb
Host	smart-fb2d0ae6-0fc4-45d4-8984-30585470d0a3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753608756 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2753608756
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1926994576
Short name	T56
Test name
Test status
Simulation time	69583462 ps
CPU time	0.99 seconds
Started	Jan 10 01:09:45 PM PST 24
Finished	Jan 10 01:10:52 PM PST 24
Peak memory	202256 kb
Host	smart-735d40e5-f392-45ef-9ea9-e63352a523a4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926994576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1926994576
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.3660403636
Short name	T79
Test name
Test status
Simulation time	26234783 ps
CPU time	0.59 seconds
Started	Jan 10 01:09:30 PM PST 24
Finished	Jan 10 01:10:35 PM PST 24
Peak memory	201372 kb
Host	smart-6eba943a-72b1-4fee-bf68-aced7c9e15d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3660403636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3660403636
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1398391205
Short name	T130
Test name
Test status
Simulation time	103488093 ps
CPU time	1.41 seconds
Started	Jan 10 01:09:22 PM PST 24
Finished	Jan 10 01:10:29 PM PST 24
Peak memory	202244 kb
Host	smart-bc56619e-fe98-4bb4-a769-f6da790a3c50
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1398391205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1398391205
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2229622655
Short name	T28
Test name
Test status
Simulation time	37436112 ps
CPU time	0.89 seconds
Started	Jan 10 01:09:35 PM PST 24
Finished	Jan 10 01:10:41 PM PST 24
Peak memory	202356 kb
Host	smart-866f5798-7ddf-4771-b85f-d9bba9763cac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229622655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.2229622655
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1601951010
Short name	T131
Test name
Test status
Simulation time	140432342 ps
CPU time	1.6 seconds
Started	Jan 10 01:09:44 PM PST 24
Finished	Jan 10 01:10:53 PM PST 24
Peak memory	202272 kb
Host	smart-8c7a40d3-83e5-4309-bc03-e82d8ccacdbe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1601951010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1601951010
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.135393783
Short name	T136
Test name
Test status
Simulation time	73941797 ps
CPU time	1.94 seconds
Started	Jan 10 01:09:27 PM PST 24
Finished	Jan 10 01:10:33 PM PST 24
Peak memory	202248 kb
Host	smart-ea9f4901-5622-42ef-80cf-3a6b1ed1faee
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135393783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.135393783
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1993113119
Short name	T38
Test name
Test status
Simulation time	193219358 ps
CPU time	4.49 seconds
Started	Jan 10 01:09:44 PM PST 24
Finished	Jan 10 01:10:55 PM PST 24
Peak memory	202140 kb
Host	smart-7d086c51-e8a3-467b-a62c-a7950e59233e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993113119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1993113119
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3640017302
Short name	T94
Test name
Test status
Simulation time	41554158 ps
CPU time	1.04 seconds
Started	Jan 10 01:09:22 PM PST 24
Finished	Jan 10 01:10:28 PM PST 24
Peak memory	210600 kb
Host	smart-12064c36-edf9-4327-9784-161e7401186b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640017302 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.3640017302
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3670083244
Short name	T51
Test name
Test status
Simulation time	77416085 ps
CPU time	1.03 seconds
Started	Jan 10 01:09:26 PM PST 24
Finished	Jan 10 01:10:34 PM PST 24
Peak memory	202420 kb
Host	smart-272dced0-bcb0-4623-8045-f526a7e37894
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670083244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3670083244
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1532770905
Short name	T61
Test name
Test status
Simulation time	103906974 ps
CPU time	1.33 seconds
Started	Jan 10 01:09:36 PM PST 24
Finished	Jan 10 01:10:43 PM PST 24
Peak memory	202236 kb
Host	smart-30ec1f3f-2157-4217-ab2d-5949c346decc
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1532770905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1532770905
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.962961082
Short name	T13
Test name
Test status
Simulation time	154668704 ps
CPU time	3.84 seconds
Started	Jan 10 01:09:25 PM PST 24
Finished	Jan 10 01:10:33 PM PST 24
Peak memory	202244 kb
Host	smart-1a15e972-d345-461f-9a18-b99b25b183ca
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=962961082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.962961082
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3868574326
Short name	T41
Test name
Test status
Simulation time	43469781 ps
CPU time	0.96 seconds
Started	Jan 10 01:09:25 PM PST 24
Finished	Jan 10 01:10:31 PM PST 24
Peak memory	202372 kb
Host	smart-610c6426-1562-4769-95e0-2b6b4338364f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868574326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.3868574326
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1463151259
Short name	T109
Test name
Test status
Simulation time	47492656 ps
CPU time	1.67 seconds
Started	Jan 10 01:09:54 PM PST 24
Finished	Jan 10 01:11:01 PM PST 24
Peak memory	202372 kb
Host	smart-a918eb0b-70a3-4f1d-a359-807f0adc6364
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1463151259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1463151259
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2158119481
Short name	T46
Test name
Test status
Simulation time	313990124 ps
CPU time	2.86 seconds
Started	Jan 10 01:09:45 PM PST 24
Finished	Jan 10 01:10:55 PM PST 24
Peak memory	202348 kb
Host	smart-e629784f-368c-4717-b4c6-525386651e1e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2158119481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2158119481
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.511174407
Short name	T42
Test name
Test status
Simulation time	25083480 ps
CPU time	1.14 seconds
Started	Jan 10 01:09:39 PM PST 24
Finished	Jan 10 01:10:46 PM PST 24
Peak memory	210544 kb
Host	smart-eb9a5198-8680-4d65-baaa-c933c3c25200
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511174407 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.511174407
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3533704739
Short name	T132
Test name
Test status
Simulation time	27693883 ps
CPU time	0.79 seconds
Started	Jan 10 01:09:33 PM PST 24
Finished	Jan 10 01:10:39 PM PST 24
Peak memory	202068 kb
Host	smart-2c83d4c4-88f3-4502-b59a-6bcae5ae8a47
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533704739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3533704739
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.409113365
Short name	T74
Test name
Test status
Simulation time	29329659 ps
CPU time	0.61 seconds
Started	Jan 10 01:09:57 PM PST 24
Finished	Jan 10 01:11:04 PM PST 24
Peak memory	201376 kb
Host	smart-966c55ff-e2a0-455e-aa33-d9849d322259
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=409113365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.409113365
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3009975575
Short name	T100
Test name
Test status
Simulation time	120205866 ps
CPU time	1.43 seconds
Started	Jan 10 01:09:37 PM PST 24
Finished	Jan 10 01:10:43 PM PST 24
Peak memory	202340 kb
Host	smart-a9742b8c-8f2f-49c1-85b4-547cad927367
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009975575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.3009975575
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1798910807
Short name	T9
Test name
Test status
Simulation time	49841469 ps
CPU time	1.07 seconds
Started	Jan 10 01:09:36 PM PST 24
Finished	Jan 10 01:10:42 PM PST 24
Peak memory	202400 kb
Host	smart-10136415-01e4-4651-a351-6878dced01a7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798910807 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.1798910807
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2892988906
Short name	T66
Test name
Test status
Simulation time	80690203 ps
CPU time	0.81 seconds
Started	Jan 10 01:09:52 PM PST 24
Finished	Jan 10 01:11:04 PM PST 24
Peak memory	202068 kb
Host	smart-f8fc6544-2da4-42e8-9c02-41fa1f221b61
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892988906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2892988906
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1566853034
Short name	T23
Test name
Test status
Simulation time	61746896 ps
CPU time	0.64 seconds
Started	Jan 10 01:09:44 PM PST 24
Finished	Jan 10 01:10:52 PM PST 24
Peak memory	201348 kb
Host	smart-d997fb84-e5e9-4860-be5e-ae97b2741b62
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1566853034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1566853034
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2234545032
Short name	T129
Test name
Test status
Simulation time	270196898 ps
CPU time	2.76 seconds
Started	Jan 10 01:09:37 PM PST 24
Finished	Jan 10 01:10:45 PM PST 24
Peak memory	202256 kb
Host	smart-f4c46c07-788d-459f-a134-1261a39af5f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2234545032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2234545032
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3726057096
Short name	T4
Test name
Test status
Simulation time	29530748 ps
CPU time	1.08 seconds
Started	Jan 10 01:09:49 PM PST 24
Finished	Jan 10 01:10:56 PM PST 24
Peak memory	202288 kb
Host	smart-1749e550-d8a1-4e3f-bb03-453cad4551be
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726057096 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.3726057096
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3047393271
Short name	T97
Test name
Test status
Simulation time	30673445 ps
CPU time	0.76 seconds
Started	Jan 10 01:09:45 PM PST 24
Finished	Jan 10 01:10:52 PM PST 24
Peak memory	202060 kb
Host	smart-dd2d944f-28e3-4bf4-a66f-34a27f48d7ad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047393271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3047393271
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.3360270519
Short name	T128
Test name
Test status
Simulation time	31699887 ps
CPU time	0.64 seconds
Started	Jan 10 01:09:50 PM PST 24
Finished	Jan 10 01:10:56 PM PST 24
Peak memory	201336 kb
Host	smart-ac63ecb4-81ca-4bc5-ba2c-c2f58dccf67e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3360270519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3360270519
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.432461994
Short name	T68
Test name
Test status
Simulation time	92115101 ps
CPU time	1.08 seconds
Started	Jan 10 01:09:33 PM PST 24
Finished	Jan 10 01:10:39 PM PST 24
Peak memory	202260 kb
Host	smart-749db020-b293-4d29-85d4-db9ecc69e06c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432461994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_c sr_outstanding.432461994
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2745042633
Short name	T32
Test name
Test status
Simulation time	156100496 ps
CPU time	1.57 seconds
Started	Jan 10 01:09:35 PM PST 24
Finished	Jan 10 01:10:41 PM PST 24
Peak memory	202160 kb
Host	smart-f09f02ab-9294-4f01-88f0-ee312dbbf4ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2745042633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2745042633
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.732452445
Short name	T33
Test name
Test status
Simulation time	256530894 ps
CPU time	4.34 seconds
Started	Jan 10 01:09:35 PM PST 24
Finished	Jan 10 01:10:44 PM PST 24
Peak memory	202320 kb
Host	smart-4d0221b3-0ced-42e6-a770-e7a6c74a4142
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=732452445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.732452445
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2411533930
Short name	T14
Test name
Test status
Simulation time	39124875 ps
CPU time	1.04 seconds
Started	Jan 10 01:09:36 PM PST 24
Finished	Jan 10 01:10:42 PM PST 24
Peak memory	202324 kb
Host	smart-0fe115f3-062c-453b-97ac-7b69b9333679
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411533930 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.2411533930
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1848161737
Short name	T60
Test name
Test status
Simulation time	26138057 ps
CPU time	0.73 seconds
Started	Jan 10 01:09:35 PM PST 24
Finished	Jan 10 01:10:40 PM PST 24
Peak memory	202048 kb
Host	smart-51ed66a4-c967-40dc-bc08-640f80a05535
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848161737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1848161737
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3639712966
Short name	T122
Test name
Test status
Simulation time	134494905 ps
CPU time	1.79 seconds
Started	Jan 10 01:09:32 PM PST 24
Finished	Jan 10 01:10:39 PM PST 24
Peak memory	202320 kb
Host	smart-21b278f3-2014-46e6-be38-f56c238e7f75
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3639712966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3639712966
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3797119698
Short name	T103
Test name
Test status
Simulation time	59952352 ps
CPU time	1.54 seconds
Started	Jan 10 01:09:47 PM PST 24
Finished	Jan 10 01:10:55 PM PST 24
Peak memory	218672 kb
Host	smart-8ac4c510-38d1-4bf0-8f14-1f34633a637d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797119698 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.3797119698
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3322287501
Short name	T25
Test name
Test status
Simulation time	22827634 ps
CPU time	0.61 seconds
Started	Jan 10 01:09:59 PM PST 24
Finished	Jan 10 01:11:07 PM PST 24
Peak memory	201460 kb
Host	smart-d2e63a4b-7dfc-415f-9e59-3b85c0f79cf7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3322287501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3322287501
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2301297280
Short name	T40
Test name
Test status
Simulation time	74820111 ps
CPU time	1.03 seconds
Started	Jan 10 01:10:00 PM PST 24
Finished	Jan 10 01:11:09 PM PST 24
Peak memory	202432 kb
Host	smart-fd53b376-fbd6-494b-aa92-a9b2a9d8b696
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301297280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.2301297280
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1658858538
Short name	T118
Test name
Test status
Simulation time	49852132 ps
CPU time	1.13 seconds
Started	Jan 10 01:10:00 PM PST 24
Finished	Jan 10 01:11:08 PM PST 24
Peak memory	202336 kb
Host	smart-1a1b4c33-ce2c-4345-bc45-b2c5c2cbe653
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1658858538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1658858538
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2412013513
Short name	T138
Test name
Test status
Simulation time	77757714 ps
CPU time	1.51 seconds
Started	Jan 10 01:09:50 PM PST 24
Finished	Jan 10 01:10:57 PM PST 24
Peak memory	210652 kb
Host	smart-2ea82072-e5fd-49f0-a0c8-f1315c48a631
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412013513 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.2412013513
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1665247355
Short name	T95
Test name
Test status
Simulation time	62835993 ps
CPU time	1.01 seconds
Started	Jan 10 01:09:46 PM PST 24
Finished	Jan 10 01:10:53 PM PST 24
Peak memory	202404 kb
Host	smart-56860320-0e00-4f70-a27b-576aacefcd7f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665247355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1665247355
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2207217884
Short name	T6
Test name
Test status
Simulation time	43323952 ps
CPU time	0.95 seconds
Started	Jan 10 01:09:53 PM PST 24
Finished	Jan 10 01:11:00 PM PST 24
Peak memory	202216 kb
Host	smart-2902900a-10a9-4281-a312-1afb3f4f69db
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207217884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.2207217884
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4026011292
Short name	T119
Test name
Test status
Simulation time	171568734 ps
CPU time	2.2 seconds
Started	Jan 10 01:10:06 PM PST 24
Finished	Jan 10 01:11:21 PM PST 24
Peak memory	202160 kb
Host	smart-0db6c164-631b-4749-8b91-c8b6fdc533e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4026011292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.4026011292
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3853974808
Short name	T44
Test name
Test status
Simulation time	285571567 ps
CPU time	2.74 seconds
Started	Jan 10 01:10:07 PM PST 24
Finished	Jan 10 01:11:20 PM PST 24
Peak memory	202140 kb
Host	smart-6e98bb26-0d14-4266-b6e2-f21652bce504
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3853974808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3853974808
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1696633285
Short name	T11
Test name
Test status
Simulation time	43080348 ps
CPU time	1.46 seconds
Started	Jan 10 01:10:10 PM PST 24
Finished	Jan 10 01:11:23 PM PST 24
Peak memory	210548 kb
Host	smart-62d5ab6b-f2d2-402d-9036-04c99a86c103
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696633285 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.1696633285
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.735589608
Short name	T98
Test name
Test status
Simulation time	46583772 ps
CPU time	0.79 seconds
Started	Jan 10 01:09:52 PM PST 24
Finished	Jan 10 01:10:58 PM PST 24
Peak memory	202032 kb
Host	smart-01f4ddd6-db27-4bd1-9f20-88321851d07b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735589608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.735589608
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1194731092
Short name	T96
Test name
Test status
Simulation time	74831067 ps
CPU time	0.98 seconds
Started	Jan 10 01:10:14 PM PST 24
Finished	Jan 10 01:11:28 PM PST 24
Peak memory	202240 kb
Host	smart-c08f1745-52ac-4d33-b69d-f203a1484835
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194731092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.1194731092
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1561212357
Short name	T36
Test name
Test status
Simulation time	98651496 ps
CPU time	2.72 seconds
Started	Jan 10 01:09:54 PM PST 24
Finished	Jan 10 01:11:03 PM PST 24
Peak memory	202316 kb
Host	smart-1aac1ada-c19e-41b3-99f3-67e67efae9b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1561212357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1561212357
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1969800920
Short name	T93
Test name
Test status
Simulation time	82600504 ps
CPU time	1.3 seconds
Started	Jan 10 01:09:45 PM PST 24
Finished	Jan 10 01:10:53 PM PST 24
Peak memory	210540 kb
Host	smart-c9c47dd7-07d2-485c-a3c0-054c54b1eb69
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969800920 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.1969800920
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1485278770
Short name	T113
Test name
Test status
Simulation time	31314082 ps
CPU time	0.95 seconds
Started	Jan 10 01:10:01 PM PST 24
Finished	Jan 10 01:11:10 PM PST 24
Peak memory	202256 kb
Host	smart-4ea174ce-8998-40fa-a96b-c46ae595a443
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485278770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1485278770
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1074701550
Short name	T75
Test name
Test status
Simulation time	23693228 ps
CPU time	0.65 seconds
Started	Jan 10 01:10:18 PM PST 24
Finished	Jan 10 01:11:33 PM PST 24
Peak memory	201308 kb
Host	smart-60017db3-6fb8-4de1-906f-ac72eabf81cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1074701550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1074701550
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3125960700
Short name	T107
Test name
Test status
Simulation time	70797207 ps
CPU time	1 seconds
Started	Jan 10 01:10:13 PM PST 24
Finished	Jan 10 01:11:32 PM PST 24
Peak memory	202356 kb
Host	smart-a4b772de-421b-4f07-a560-7dab2395a0a8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125960700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.3125960700
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.985915384
Short name	T112
Test name
Test status
Simulation time	51939357 ps
CPU time	1.27 seconds
Started	Jan 10 01:10:16 PM PST 24
Finished	Jan 10 01:11:30 PM PST 24
Peak memory	202228 kb
Host	smart-2b0673f1-bfa5-44ba-850f-c7523469f404
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=985915384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.985915384
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.573979780
Short name	T104
Test name
Test status
Simulation time	39385722 ps
CPU time	1.01 seconds
Started	Jan 10 01:09:52 PM PST 24
Finished	Jan 10 01:10:59 PM PST 24
Peak memory	202380 kb
Host	smart-f0096a54-1ade-474b-840b-882671be2c7a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573979780 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.573979780
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2013692845
Short name	T39
Test name
Test status
Simulation time	63551124 ps
CPU time	0.97 seconds
Started	Jan 10 01:10:03 PM PST 24
Finished	Jan 10 01:11:12 PM PST 24
Peak memory	202440 kb
Host	smart-4e70be15-193d-450b-b02e-33578f1cbcad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013692845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2013692845
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.4124372503
Short name	T117
Test name
Test status
Simulation time	27722952 ps
CPU time	0.64 seconds
Started	Jan 10 01:09:57 PM PST 24
Finished	Jan 10 01:11:05 PM PST 24
Peak memory	201272 kb
Host	smart-e2dc2a4d-c497-44e6-93db-df12cafc4e4c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4124372503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.4124372503
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4094853412
Short name	T27
Test name
Test status
Simulation time	61698068 ps
CPU time	1.24 seconds
Started	Jan 10 01:10:00 PM PST 24
Finished	Jan 10 01:11:10 PM PST 24
Peak memory	202352 kb
Host	smart-5975a9bb-48db-4ef2-b9f1-83aa499000da
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094853412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.4094853412
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.642625226
Short name	T134
Test name
Test status
Simulation time	153255904 ps
CPU time	1.79 seconds
Started	Jan 10 01:10:22 PM PST 24
Finished	Jan 10 01:11:40 PM PST 24
Peak memory	202384 kb
Host	smart-5440872b-53d7-4131-9c48-746d0eb8ff0d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=642625226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.642625226
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1259350718
Short name	T102
Test name
Test status
Simulation time	42545446 ps
CPU time	0.9 seconds
Started	Jan 10 01:09:50 PM PST 24
Finished	Jan 10 01:10:57 PM PST 24
Peak memory	202268 kb
Host	smart-2d3bdebf-ffca-4c2d-9d70-3a2475af9c9b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259350718 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.1259350718
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1234112697
Short name	T57
Test name
Test status
Simulation time	73117762 ps
CPU time	1.01 seconds
Started	Jan 10 01:10:08 PM PST 24
Finished	Jan 10 01:11:20 PM PST 24
Peak memory	202288 kb
Host	smart-4a03e2fb-69ac-4cdc-8f86-9f339b098eea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234112697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1234112697
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2776195861
Short name	T125
Test name
Test status
Simulation time	24318224 ps
CPU time	0.64 seconds
Started	Jan 10 01:10:08 PM PST 24
Finished	Jan 10 01:11:20 PM PST 24
Peak memory	201320 kb
Host	smart-2f2dbc32-bf86-4e23-a2cd-d82ca8452f28
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2776195861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2776195861
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2479355429
Short name	T89
Test name
Test status
Simulation time	128153270 ps
CPU time	1.51 seconds
Started	Jan 10 01:09:57 PM PST 24
Finished	Jan 10 01:11:05 PM PST 24
Peak memory	202200 kb
Host	smart-7975031d-0d7e-4b37-a5e7-82d7597c9a21
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479355429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.2479355429
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.50912025
Short name	T47
Test name
Test status
Simulation time	54043820 ps
CPU time	1.43 seconds
Started	Jan 10 01:09:44 PM PST 24
Finished	Jan 10 01:10:52 PM PST 24
Peak memory	202444 kb
Host	smart-a4fcf95a-f015-45a5-9558-353e25d00098
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=50912025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.50912025
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2160308199
Short name	T105
Test name
Test status
Simulation time	302407317 ps
CPU time	3.05 seconds
Started	Jan 10 01:09:53 PM PST 24
Finished	Jan 10 01:11:02 PM PST 24
Peak memory	202360 kb
Host	smart-2651d610-8112-4057-b2d5-aac2f4d969ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2160308199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2160308199
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1048691320
Short name	T37
Test name
Test status
Simulation time	52295420 ps
CPU time	1.3 seconds
Started	Jan 10 01:09:34 PM PST 24
Finished	Jan 10 01:10:41 PM PST 24
Peak memory	210548 kb
Host	smart-5089dfb8-3aee-48ce-a081-f6fe228070d6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048691320 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.1048691320
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3163895827
Short name	T120
Test name
Test status
Simulation time	36372167 ps
CPU time	0.96 seconds
Started	Jan 10 01:09:35 PM PST 24
Finished	Jan 10 01:10:40 PM PST 24
Peak memory	202316 kb
Host	smart-26a6aa3d-6f2d-4f0b-9b2d-31f67ff09c0b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163895827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3163895827
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.1167825016
Short name	T77
Test name
Test status
Simulation time	25088718 ps
CPU time	0.62 seconds
Started	Jan 10 01:09:28 PM PST 24
Finished	Jan 10 01:10:34 PM PST 24
Peak memory	201384 kb
Host	smart-e1da2676-c74e-446e-bd98-a137d408aadf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1167825016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1167825016
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3655895321
Short name	T58
Test name
Test status
Simulation time	88202611 ps
CPU time	1.36 seconds
Started	Jan 10 01:09:32 PM PST 24
Finished	Jan 10 01:10:39 PM PST 24
Peak memory	202224 kb
Host	smart-a4bf4a14-ab6a-462c-b59b-4c2fa7a5bcbe
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3655895321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3655895321
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2702777876
Short name	T92
Test name
Test status
Simulation time	86551915 ps
CPU time	2.32 seconds
Started	Jan 10 01:09:38 PM PST 24
Finished	Jan 10 01:10:45 PM PST 24
Peak memory	202292 kb
Host	smart-28df6cce-71b9-424b-85fb-1f6def6479ac
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2702777876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2702777876
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2025105992
Short name	T147
Test name
Test status
Simulation time	90321098 ps
CPU time	1.1 seconds
Started	Jan 10 01:09:50 PM PST 24
Finished	Jan 10 01:10:57 PM PST 24
Peak memory	202336 kb
Host	smart-bac16d6d-62cd-4e5f-b7f5-71ffc8367acf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025105992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c sr_outstanding.2025105992
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.70965402
Short name	T12
Test name
Test status
Simulation time	286128615 ps
CPU time	2.25 seconds
Started	Jan 10 01:09:44 PM PST 24
Finished	Jan 10 01:10:53 PM PST 24
Peak memory	202284 kb
Host	smart-ef29d399-23ac-481c-99c5-3df8ec085085
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=70965402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.70965402
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2094092403
Short name	T70
Test name
Test status
Simulation time	294830930 ps
CPU time	4.17 seconds
Started	Jan 10 01:09:35 PM PST 24
Finished	Jan 10 01:10:43 PM PST 24
Peak memory	202440 kb
Host	smart-29659782-8737-470e-b548-01d73b5e76bf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2094092403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2094092403
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.1454239619
Short name	T110
Test name
Test status
Simulation time	22113255 ps
CPU time	0.63 seconds
Started	Jan 10 01:10:11 PM PST 24
Finished	Jan 10 01:11:23 PM PST 24
Peak memory	201416 kb
Host	smart-b3e775ed-94ad-49c4-be02-8e34a5c51144
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1454239619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1454239619
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2131804981
Short name	T82
Test name
Test status
Simulation time	45524959 ps
CPU time	0.66 seconds
Started	Jan 10 01:10:09 PM PST 24
Finished	Jan 10 01:11:22 PM PST 24
Peak memory	201360 kb
Host	smart-515caad6-795a-4dab-a0b4-76687a09e35b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2131804981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2131804981
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.1605572608
Short name	T26
Test name
Test status
Simulation time	26854123 ps
CPU time	0.6 seconds
Started	Jan 10 01:10:06 PM PST 24
Finished	Jan 10 01:11:17 PM PST 24
Peak memory	201368 kb
Host	smart-c76152cf-97e2-4f5f-b94b-b78033149706
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1605572608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1605572608
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.591413675
Short name	T71
Test name
Test status
Simulation time	28042488 ps
CPU time	0.65 seconds
Started	Jan 10 01:09:46 PM PST 24
Finished	Jan 10 01:10:53 PM PST 24
Peak memory	201232 kb
Host	smart-9564a1c7-e60f-4625-a53d-5eb76962f8af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=591413675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.591413675
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.342577880
Short name	T135
Test name
Test status
Simulation time	43682389 ps
CPU time	0.66 seconds
Started	Jan 10 01:09:52 PM PST 24
Finished	Jan 10 01:10:58 PM PST 24
Peak memory	201416 kb
Host	smart-af5fc228-9289-48e7-87de-028780228d8a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=342577880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.342577880
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1585219697
Short name	T111
Test name
Test status
Simulation time	42971129 ps
CPU time	0.63 seconds
Started	Jan 10 01:09:58 PM PST 24
Finished	Jan 10 01:11:05 PM PST 24
Peak memory	201168 kb
Host	smart-488b2e89-027f-49de-a8ec-8abb955f501f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1585219697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1585219697
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.4275885105
Short name	T108
Test name
Test status
Simulation time	57128738 ps
CPU time	0.66 seconds
Started	Jan 10 01:09:59 PM PST 24
Finished	Jan 10 01:11:07 PM PST 24
Peak memory	201416 kb
Host	smart-5a63d41b-6eab-4ff0-8f70-4391be1a8f9e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4275885105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.4275885105
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3118700035
Short name	T101
Test name
Test status
Simulation time	164203679 ps
CPU time	2.01 seconds
Started	Jan 10 01:09:36 PM PST 24
Finished	Jan 10 01:10:43 PM PST 24
Peak memory	202412 kb
Host	smart-93f786e1-8f18-4051-a9d7-193f3a0258af
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118700035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3118700035
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3138672642
Short name	T59
Test name
Test status
Simulation time	479408270 ps
CPU time	8.84 seconds
Started	Jan 10 01:09:38 PM PST 24
Finished	Jan 10 01:10:53 PM PST 24
Peak memory	202344 kb
Host	smart-28228075-b78d-4e1f-bc89-97572cf6a374
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138672642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3138672642
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3507198865
Short name	T3
Test name
Test status
Simulation time	54758435 ps
CPU time	1.11 seconds
Started	Jan 10 01:09:41 PM PST 24
Finished	Jan 10 01:10:48 PM PST 24
Peak memory	202292 kb
Host	smart-e2e39806-c78a-40e8-bd2f-73b938aa6664
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507198865 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.3507198865
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1357934073
Short name	T114
Test name
Test status
Simulation time	22328310 ps
CPU time	0.72 seconds
Started	Jan 10 01:09:54 PM PST 24
Finished	Jan 10 01:11:06 PM PST 24
Peak memory	202004 kb
Host	smart-964f1147-fb4f-4c34-8e2a-1f9a6c1d4d7b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357934073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1357934073
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3886826539
Short name	T53
Test name
Test status
Simulation time	45580446 ps
CPU time	1.36 seconds
Started	Jan 10 01:09:33 PM PST 24
Finished	Jan 10 01:10:40 PM PST 24
Peak memory	202156 kb
Host	smart-e7c7d128-e769-49bf-8228-11c0860b232e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3886826539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3886826539
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.131342717
Short name	T99
Test name
Test status
Simulation time	174037650 ps
CPU time	3.92 seconds
Started	Jan 10 01:09:44 PM PST 24
Finished	Jan 10 01:10:54 PM PST 24
Peak memory	202096 kb
Host	smart-295fe4a6-d582-4665-b557-5807855ad80c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=131342717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.131342717
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3033782038
Short name	T91
Test name
Test status
Simulation time	33577267 ps
CPU time	0.95 seconds
Started	Jan 10 01:09:38 PM PST 24
Finished	Jan 10 01:10:44 PM PST 24
Peak memory	202424 kb
Host	smart-3d9eda51-91ee-45f9-8a8a-2a0b4ac15fc4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033782038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.3033782038
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3664871117
Short name	T35
Test name
Test status
Simulation time	461202925 ps
CPU time	3.06 seconds
Started	Jan 10 01:09:54 PM PST 24
Finished	Jan 10 01:11:02 PM PST 24
Peak memory	202348 kb
Host	smart-3ceff4d7-96da-4f38-bfaa-12080748ac95
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3664871117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3664871117
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3044721478
Short name	T80
Test name
Test status
Simulation time	51590060 ps
CPU time	0.64 seconds
Started	Jan 10 01:10:06 PM PST 24
Finished	Jan 10 01:11:19 PM PST 24
Peak memory	201272 kb
Host	smart-a0aaaabd-67af-447d-afcb-cef1d37b647a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3044721478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3044721478
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3591306002
Short name	T78
Test name
Test status
Simulation time	23676769 ps
CPU time	0.61 seconds
Started	Jan 10 01:09:54 PM PST 24
Finished	Jan 10 01:11:00 PM PST 24
Peak memory	201332 kb
Host	smart-a4a418d1-f8b6-4ebf-b7ed-62feeaa82aaf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3591306002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3591306002
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.1533010270
Short name	T143
Test name
Test status
Simulation time	30023674 ps
CPU time	0.64 seconds
Started	Jan 10 01:09:58 PM PST 24
Finished	Jan 10 01:11:06 PM PST 24
Peak memory	201392 kb
Host	smart-b55ce5c5-5623-4506-8cda-aadd4554a336
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1533010270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1533010270
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.220195281
Short name	T115
Test name
Test status
Simulation time	24042695 ps
CPU time	0.64 seconds
Started	Jan 10 01:10:15 PM PST 24
Finished	Jan 10 01:11:28 PM PST 24
Peak memory	201456 kb
Host	smart-b0291b6e-116f-4ca7-93fc-171a6989ab49
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=220195281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.220195281
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3545511480
Short name	T148
Test name
Test status
Simulation time	32613624 ps
CPU time	0.65 seconds
Started	Jan 10 01:10:14 PM PST 24
Finished	Jan 10 01:11:27 PM PST 24
Peak memory	201356 kb
Host	smart-afe1d9ee-e86c-4df4-bac1-f3ab1fc86b3e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3545511480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3545511480
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2092422517
Short name	T127
Test name
Test status
Simulation time	20625605 ps
CPU time	0.61 seconds
Started	Jan 10 01:10:11 PM PST 24
Finished	Jan 10 01:11:24 PM PST 24
Peak memory	201460 kb
Host	smart-9d25baeb-7aa5-4da1-9a20-36a878658774
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2092422517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2092422517
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1976034035
Short name	T55
Test name
Test status
Simulation time	116917635 ps
CPU time	3.09 seconds
Started	Jan 10 01:09:32 PM PST 24
Finished	Jan 10 01:10:41 PM PST 24
Peak memory	202364 kb
Host	smart-4c590eaf-9f52-4c0f-8f29-dc58783cee66
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976034035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1976034035
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3389969501
Short name	T17
Test name
Test status
Simulation time	39236724 ps
CPU time	0.74 seconds
Started	Jan 10 01:09:39 PM PST 24
Finished	Jan 10 01:10:46 PM PST 24
Peak memory	202116 kb
Host	smart-6f110f47-0132-4b56-ae0f-3ebdd7df7ed3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389969501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3389969501
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1854983765
Short name	T146
Test name
Test status
Simulation time	54793967 ps
CPU time	1.28 seconds
Started	Jan 10 01:09:36 PM PST 24
Finished	Jan 10 01:10:43 PM PST 24
Peak memory	210548 kb
Host	smart-e1445713-8684-44bf-9301-4d39e747a6c8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854983765 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.1854983765
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3623966318
Short name	T145
Test name
Test status
Simulation time	170326638 ps
CPU time	2.22 seconds
Started	Jan 10 01:09:30 PM PST 24
Finished	Jan 10 01:10:37 PM PST 24
Peak memory	202300 kb
Host	smart-ecebe6ff-5de0-4df9-ae59-872e7d2de3bf
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3623966318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3623966318
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3235973444
Short name	T87
Test name
Test status
Simulation time	273303336 ps
CPU time	2.52 seconds
Started	Jan 10 01:09:29 PM PST 24
Finished	Jan 10 01:10:36 PM PST 24
Peak memory	202140 kb
Host	smart-371da1cc-cd12-49d0-89bc-5ea9fd1756af
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3235973444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3235973444
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2105020641
Short name	T133
Test name
Test status
Simulation time	71411596 ps
CPU time	1 seconds
Started	Jan 10 01:09:42 PM PST 24
Finished	Jan 10 01:10:49 PM PST 24
Peak memory	202324 kb
Host	smart-ad550870-26b7-4a13-bfbf-5a560da0e54b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105020641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c sr_outstanding.2105020641
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1380009776
Short name	T137
Test name
Test status
Simulation time	339546405 ps
CPU time	3.26 seconds
Started	Jan 10 01:09:38 PM PST 24
Finished	Jan 10 01:10:48 PM PST 24
Peak memory	202296 kb
Host	smart-bbe90cfc-5252-4fa6-8076-e53d8dec9214
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1380009776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1380009776
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.240766912
Short name	T141
Test name
Test status
Simulation time	130785235 ps
CPU time	2.43 seconds
Started	Jan 10 01:09:42 PM PST 24
Finished	Jan 10 01:10:51 PM PST 24
Peak memory	202384 kb
Host	smart-0a67ae23-e825-4b88-ae22-afc39ae3b2a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=240766912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.240766912
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.1201483305
Short name	T81
Test name
Test status
Simulation time	31016079 ps
CPU time	0.63 seconds
Started	Jan 10 01:10:17 PM PST 24
Finished	Jan 10 01:11:32 PM PST 24
Peak memory	201336 kb
Host	smart-540f23c3-cae9-4d4b-8be0-6bf913253cdd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1201483305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1201483305
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.1864321640
Short name	T123
Test name
Test status
Simulation time	23126909 ps
CPU time	0.63 seconds
Started	Jan 10 01:10:08 PM PST 24
Finished	Jan 10 01:11:20 PM PST 24
Peak memory	201352 kb
Host	smart-6e12523b-f811-446c-9912-04deb2c46089
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1864321640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1864321640
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.3291017890
Short name	T22
Test name
Test status
Simulation time	26124178 ps
CPU time	0.62 seconds
Started	Jan 10 01:10:06 PM PST 24
Finished	Jan 10 01:11:17 PM PST 24
Peak memory	201280 kb
Host	smart-f0d69fd6-67b9-4c8c-a76b-da385e63b766
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3291017890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3291017890
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.485510499
Short name	T84
Test name
Test status
Simulation time	31756144 ps
CPU time	0.69 seconds
Started	Jan 10 01:10:17 PM PST 24
Finished	Jan 10 01:11:36 PM PST 24
Peak memory	201392 kb
Host	smart-fe663c21-bc26-4e82-8788-c479d8c6913a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=485510499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.485510499
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2017628791
Short name	T116
Test name
Test status
Simulation time	61073904 ps
CPU time	0.65 seconds
Started	Jan 10 01:09:52 PM PST 24
Finished	Jan 10 01:10:59 PM PST 24
Peak memory	201428 kb
Host	smart-27fa6e43-4ef8-452e-b120-547a7a168e69
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2017628791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2017628791
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.202411211
Short name	T24
Test name
Test status
Simulation time	23452414 ps
CPU time	0.63 seconds
Started	Jan 10 01:09:57 PM PST 24
Finished	Jan 10 01:11:04 PM PST 24
Peak memory	201412 kb
Host	smart-8ff4260d-565a-4cfe-9408-e5c44d397287
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=202411211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.202411211
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1202236660
Short name	T140
Test name
Test status
Simulation time	31386944 ps
CPU time	0.94 seconds
Started	Jan 10 01:09:46 PM PST 24
Finished	Jan 10 01:10:54 PM PST 24
Peak memory	202288 kb
Host	smart-d04734a1-843b-415e-b424-8961d8f859d4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202236660 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1202236660
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3386007440
Short name	T7
Test name
Test status
Simulation time	62869592 ps
CPU time	0.98 seconds
Started	Jan 10 01:09:49 PM PST 24
Finished	Jan 10 01:10:56 PM PST 24
Peak memory	202356 kb
Host	smart-830f3fb0-6d05-46e1-9f54-2c2df03edc5c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386007440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3386007440
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2774503335
Short name	T50
Test name
Test status
Simulation time	58794517 ps
CPU time	1.27 seconds
Started	Jan 10 01:09:47 PM PST 24
Finished	Jan 10 01:10:55 PM PST 24
Peak memory	202284 kb
Host	smart-870467f2-ef1c-4f6c-95c3-f7cdc24904d4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774503335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.2774503335
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3683075061
Short name	T15
Test name
Test status
Simulation time	92297926 ps
CPU time	1.37 seconds
Started	Jan 10 01:09:40 PM PST 24
Finished	Jan 10 01:10:47 PM PST 24
Peak memory	202392 kb
Host	smart-59155adb-af2c-46ac-b917-a39a5b4376dc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3683075061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3683075061
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.958641276
Short name	T86
Test name
Test status
Simulation time	31617315 ps
CPU time	0.97 seconds
Started	Jan 10 01:09:32 PM PST 24
Finished	Jan 10 01:10:38 PM PST 24
Peak memory	202372 kb
Host	smart-fafe5041-faca-4bdd-8292-3af9d4d3e51e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958641276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.958641276
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3452350974
Short name	T29
Test name
Test status
Simulation time	107658112 ps
CPU time	1.39 seconds
Started	Jan 10 01:10:01 PM PST 24
Finished	Jan 10 01:11:10 PM PST 24
Peak memory	202168 kb
Host	smart-ff8bb13f-fa33-46d8-aa8d-7ab3b28ec9fe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452350974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.3452350974
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2938448861
Short name	T64
Test name
Test status
Simulation time	274075946 ps
CPU time	2.67 seconds
Started	Jan 10 01:09:42 PM PST 24
Finished	Jan 10 01:10:55 PM PST 24
Peak memory	202332 kb
Host	smart-dfed0711-fb5b-4c24-a889-4ac6986deacf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2938448861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2938448861
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1151518943
Short name	T48
Test name
Test status
Simulation time	277857149 ps
CPU time	2.72 seconds
Started	Jan 10 01:10:01 PM PST 24
Finished	Jan 10 01:11:12 PM PST 24
Peak memory	202188 kb
Host	smart-85bf604a-44b7-4623-86b3-fbbc27789418
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1151518943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1151518943
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1799310210
Short name	T90
Test name
Test status
Simulation time	45674665 ps
CPU time	1.49 seconds
Started	Jan 10 01:09:47 PM PST 24
Finished	Jan 10 01:10:55 PM PST 24
Peak memory	218556 kb
Host	smart-5f6e4637-7655-45a8-b30c-5e043ed8cbff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799310210 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1799310210
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2706869823
Short name	T69
Test name
Test status
Simulation time	68472270 ps
CPU time	1 seconds
Started	Jan 10 01:09:33 PM PST 24
Finished	Jan 10 01:10:39 PM PST 24
Peak memory	202448 kb
Host	smart-0368dbc8-d5e1-4300-9a55-f94296347309
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706869823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2706869823
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3001712329
Short name	T88
Test name
Test status
Simulation time	130407639 ps
CPU time	1.18 seconds
Started	Jan 10 01:09:32 PM PST 24
Finished	Jan 10 01:10:38 PM PST 24
Peak memory	202352 kb
Host	smart-2eb984da-dc48-4e7d-8265-6da717788e6f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001712329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c sr_outstanding.3001712329
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4208123920
Short name	T144
Test name
Test status
Simulation time	72160110 ps
CPU time	2.19 seconds
Started	Jan 10 01:09:58 PM PST 24
Finished	Jan 10 01:11:07 PM PST 24
Peak memory	202344 kb
Host	smart-a1c0739a-df30-4e71-9c3a-7922cf875aca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4208123920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.4208123920
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2204587700
Short name	T67
Test name
Test status
Simulation time	46956435 ps
CPU time	1.16 seconds
Started	Jan 10 01:10:00 PM PST 24
Finished	Jan 10 01:11:09 PM PST 24
Peak memory	210540 kb
Host	smart-2cf1b394-343a-462b-bc7e-df072ca99fa2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204587700 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.2204587700
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.616728131
Short name	T124
Test name
Test status
Simulation time	50913536 ps
CPU time	0.86 seconds
Started	Jan 10 01:09:39 PM PST 24
Finished	Jan 10 01:10:46 PM PST 24
Peak memory	202028 kb
Host	smart-89f9a8a0-4dfd-4869-9dcd-ba567e5cdd34
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616728131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.616728131
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4134844292
Short name	T54
Test name
Test status
Simulation time	43007655 ps
CPU time	1.06 seconds
Started	Jan 10 01:09:33 PM PST 24
Finished	Jan 10 01:10:39 PM PST 24
Peak memory	202388 kb
Host	smart-933b1bcd-8d47-46fc-9f7f-62a20948ec77
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134844292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.4134844292
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3387421348
Short name	T121
Test name
Test status
Simulation time	155352166 ps
CPU time	1.76 seconds
Started	Jan 10 01:09:48 PM PST 24
Finished	Jan 10 01:10:56 PM PST 24
Peak memory	202256 kb
Host	smart-c1346da6-d0ca-49f5-b98b-0cb89c54b794
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3387421348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3387421348
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1028885806
Short name	T65
Test name
Test status
Simulation time	34223304 ps
CPU time	0.95 seconds
Started	Jan 10 01:10:09 PM PST 24
Finished	Jan 10 01:11:22 PM PST 24
Peak memory	202328 kb
Host	smart-24278dfb-28dd-424a-9b3a-d1df5afd3c18
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028885806 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.1028885806
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1080388319
Short name	T8
Test name
Test status
Simulation time	27768628 ps
CPU time	0.76 seconds
Started	Jan 10 01:09:38 PM PST 24
Finished	Jan 10 01:10:44 PM PST 24
Peak memory	202052 kb
Host	smart-12b0f05a-07aa-4eb3-b7a3-9db68f4f0e41
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080388319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1080388319
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.290927136
Short name	T139
Test name
Test status
Simulation time	27701649 ps
CPU time	0.7 seconds
Started	Jan 10 01:09:36 PM PST 24
Finished	Jan 10 01:10:41 PM PST 24
Peak memory	201352 kb
Host	smart-8d0cdb49-78ab-4bcb-a883-21ad9c1ecaa7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=290927136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.290927136
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1440661835
Short name	T106
Test name
Test status
Simulation time	76800312 ps
CPU time	1.12 seconds
Started	Jan 10 01:09:32 PM PST 24
Finished	Jan 10 01:10:37 PM PST 24
Peak memory	202280 kb
Host	smart-af623615-55d3-4b29-b61e-79d5d7c92253
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440661835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.1440661835
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.132812742
Short name	T126
Test name
Test status
Simulation time	335114586 ps
CPU time	3.66 seconds
Started	Jan 10 01:09:33 PM PST 24
Finished	Jan 10 01:10:41 PM PST 24
Peak memory	202344 kb
Host	smart-c2e95e28-b9c8-487c-9558-01934bc49aa5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=132812742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.132812742
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1294366385
Short name	T43
Test name
Test status
Simulation time	445241023 ps
CPU time	2.99 seconds
Started	Jan 10 01:09:46 PM PST 24
Finished	Jan 10 01:10:55 PM PST 24
Peak memory	202392 kb
Host	smart-42b164cf-0901-4243-bc3e-a6047818753d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1294366385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1294366385
Directory	/workspace/9.usbdev_tl_intg_err/latest