Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	17	0	17	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	277	1		T5	2		T12	2		T21	5
all_pins[1]	277	1		T5	2		T12	2		T21	5
all_pins[2]	277	1		T5	2		T12	2		T21	5
all_pins[3]	277	1		T5	2		T12	2		T21	5
all_pins[4]	277	1		T5	2		T12	2		T21	5
all_pins[5]	277	1		T5	2		T12	2		T21	5
all_pins[6]	277	1		T5	2		T12	2		T21	5
all_pins[7]	277	1		T5	2		T12	2		T21	5
all_pins[8]	277	1		T5	2		T12	2		T21	5
all_pins[9]	277	1		T5	2		T12	2		T21	5
all_pins[10]	277	1		T5	2		T12	2		T21	5
all_pins[11]	277	1		T5	2		T12	2		T21	5
all_pins[12]	277	1		T5	2		T12	2		T21	5
all_pins[13]	277	1		T5	2		T12	2		T21	5
all_pins[14]	277	1		T5	2		T12	2		T21	5
all_pins[15]	277	1		T5	2		T12	2		T21	5
all_pins[16]	277	1		T5	2		T12	2		T21	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3946	1		T5	34		T12	34		T21	66
values[0x1]	763	1		T21	19		T16	14		T22	9
transitions[0x0=>0x1]	578	1		T21	14		T16	12		T22	9
transitions[0x1=>0x0]	582	1		T21	14		T16	12		T22	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	224	1		T5	2		T12	2		T21	4
all_pins[0]	values[0x1]	53	1		T21	1		T24	3		T26	2
all_pins[0]	transitions[0x0=>0x1]	45	1		T21	1		T24	3		T26	2
all_pins[0]	transitions[0x1=>0x0]	28	1		T21	1		T22	3		T25	1
all_pins[1]	values[0x0]	241	1		T5	2		T12	2		T21	4
all_pins[1]	values[0x1]	36	1		T21	1		T22	3		T25	1
all_pins[1]	transitions[0x0=>0x1]	27	1		T21	1		T22	3		T25	1
all_pins[1]	transitions[0x1=>0x0]	46	1		T21	1		T16	1		T24	4
all_pins[2]	values[0x0]	222	1		T5	2		T12	2		T21	4
all_pins[2]	values[0x1]	55	1		T21	1		T16	1		T24	4
all_pins[2]	transitions[0x0=>0x1]	39	1		T21	1		T24	3		T23	1
all_pins[2]	transitions[0x1=>0x0]	30	1		T21	2		T16	2		T22	2
all_pins[3]	values[0x0]	231	1		T5	2		T12	2		T21	3
all_pins[3]	values[0x1]	46	1		T21	2		T16	3		T22	2
all_pins[3]	transitions[0x0=>0x1]	34	1		T16	3		T22	2		T24	1
all_pins[3]	transitions[0x1=>0x0]	35	1		T21	1		T24	1		T23	2
all_pins[4]	values[0x0]	230	1		T5	2		T12	2		T21	2
all_pins[4]	values[0x1]	47	1		T21	3		T24	1		T26	1
all_pins[4]	transitions[0x0=>0x1]	36	1		T21	3		T24	1		T26	1
all_pins[4]	transitions[0x1=>0x0]	35	1		T21	1		T77	4		T72	4
all_pins[5]	values[0x0]	231	1		T5	2		T12	2		T21	4
all_pins[5]	values[0x1]	46	1		T21	1		T71	2		T77	5
all_pins[5]	transitions[0x0=>0x1]	36	1		T21	1		T77	2		T72	3
all_pins[5]	transitions[0x1=>0x0]	27	1		T22	2		T24	2		T23	4
all_pins[6]	values[0x0]	240	1		T5	2		T12	2		T21	5
all_pins[6]	values[0x1]	37	1		T22	2		T24	2		T23	4
all_pins[6]	transitions[0x0=>0x1]	25	1		T22	2		T24	1		T23	1
all_pins[6]	transitions[0x1=>0x0]	37	1		T21	1		T26	1		T73	5
all_pins[7]	values[0x0]	228	1		T5	2		T12	2		T21	4
all_pins[7]	values[0x1]	49	1		T21	1		T24	1		T26	1
all_pins[7]	transitions[0x0=>0x1]	39	1		T26	1		T23	1		T77	1
all_pins[7]	transitions[0x1=>0x0]	31	1		T21	3		T16	1		T26	1
all_pins[8]	values[0x0]	236	1		T5	2		T12	2		T21	1
all_pins[8]	values[0x1]	41	1		T21	4		T16	1		T24	1
all_pins[8]	transitions[0x0=>0x1]	34	1		T21	3		T16	1		T24	1
all_pins[8]	transitions[0x1=>0x0]	47	1		T16	3		T26	1		T25	1
all_pins[9]	values[0x0]	223	1		T5	2		T12	2		T21	4
all_pins[9]	values[0x1]	54	1		T21	1		T16	3		T26	1
all_pins[9]	transitions[0x0=>0x1]	43	1		T21	1		T16	3		T26	1
all_pins[9]	transitions[0x1=>0x0]	36	1		T21	1		T24	1		T25	2
all_pins[10]	values[0x0]	230	1		T5	2		T12	2		T21	4
all_pins[10]	values[0x1]	47	1		T21	1		T24	1		T25	2
all_pins[10]	transitions[0x0=>0x1]	34	1		T24	1		T25	2		T77	1
all_pins[10]	transitions[0x1=>0x0]	30	1		T16	1		T22	1		T25	2
all_pins[11]	values[0x0]	234	1		T5	2		T12	2		T21	4
all_pins[11]	values[0x1]	43	1		T21	1		T16	1		T22	1
all_pins[11]	transitions[0x0=>0x1]	33	1		T21	1		T22	1		T25	1
all_pins[11]	transitions[0x1=>0x0]	37	1		T16	1		T24	2		T26	4
all_pins[12]	values[0x0]	230	1		T5	2		T12	2		T21	5
all_pins[12]	values[0x1]	47	1		T16	2		T24	2		T26	4
all_pins[12]	transitions[0x0=>0x1]	32	1		T16	2		T26	4		T25	1
all_pins[12]	transitions[0x1=>0x0]	16	1		T22	1		T71	1		T72	1
all_pins[13]	values[0x0]	246	1		T5	2		T12	2		T21	5
all_pins[13]	values[0x1]	31	1		T22	1		T24	2		T23	4
all_pins[13]	transitions[0x0=>0x1]	23	1		T22	1		T23	1		T71	3
all_pins[13]	transitions[0x1=>0x0]	36	1		T21	1		T16	1		T71	1
all_pins[14]	values[0x0]	233	1		T5	2		T12	2		T21	4
all_pins[14]	values[0x1]	44	1		T21	1		T16	1		T24	2
all_pins[14]	transitions[0x0=>0x1]	33	1		T21	1		T16	1		T24	2
all_pins[14]	transitions[0x1=>0x0]	44	1		T21	1		T26	1		T71	2
all_pins[15]	values[0x0]	222	1		T5	2		T12	2		T21	4
all_pins[15]	values[0x1]	55	1		T21	1		T26	1		T71	3
all_pins[15]	transitions[0x0=>0x1]	45	1		T21	1		T26	1		T71	2
all_pins[15]	transitions[0x1=>0x0]	22	1		T16	2		T23	2		T71	1
all_pins[16]	values[0x0]	245	1		T5	2		T12	2		T21	5
all_pins[16]	values[0x1]	32	1		T16	2		T23	2		T71	2
all_pins[16]	transitions[0x0=>0x1]	20	1		T16	2		T23	1		T71	2
all_pins[16]	transitions[0x1=>0x0]	45	1		T21	1		T24	3		T26	2