Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	201	1		T21	4		T16	4		T22	4
all_values[1]	201	1		T21	4		T16	4		T22	4
all_values[2]	201	1		T21	4		T16	4		T22	4
all_values[3]	201	1		T21	4		T16	4		T22	4
all_values[4]	201	1		T21	4		T16	4		T22	4
all_values[5]	201	1		T21	4		T16	4		T22	4
all_values[6]	201	1		T21	4		T16	4		T22	4
all_values[7]	201	1		T21	4		T16	4		T22	4
all_values[8]	201	1		T21	4		T16	4		T22	4
all_values[9]	201	1		T21	4		T16	4		T22	4
all_values[10]	201	1		T21	4		T16	4		T22	4
all_values[11]	201	1		T21	4		T16	4		T22	4
all_values[12]	201	1		T21	4		T16	4		T22	4
all_values[13]	201	1		T21	4		T16	4		T22	4
all_values[14]	201	1		T21	4		T16	4		T22	4
all_values[15]	201	1		T21	4		T16	4		T22	4
all_values[16]	201	1		T21	4		T16	4		T22	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1903	1		T21	47		T16	41		T22	36
auto[1]	1514	1		T21	21		T16	27		T22	32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	588	1		T21	7		T16	16		T22	18
auto[1]	2829	1		T21	61		T16	52		T22	50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2023	1		T21	36		T16	40		T22	42
auto[1]	1394	1		T21	32		T16	28		T22	26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	24	1		T16	1		T71	1		T73	2
all_values[0]	auto[0]	auto[0]	auto[1]	33	1		T21	2		T22	1		T26	1
all_values[0]	auto[0]	auto[1]	auto[0]	10	1		T16	1		T22	2		T71	1
all_values[0]	auto[0]	auto[1]	auto[1]	35	1		T16	1		T24	2		T23	1
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T21	1		T16	1		T24	1
all_values[0]	auto[1]	auto[1]	auto[1]	43	1		T21	1		T22	1		T24	1
all_values[1]	auto[0]	auto[0]	auto[0]	25	1		T16	1		T26	1		T73	1
all_values[1]	auto[0]	auto[0]	auto[1]	41	1		T21	2		T16	1		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	15	1		T16	1		T26	3		T23	1
all_values[1]	auto[0]	auto[1]	auto[1]	41	1		T22	2		T24	1		T71	3
all_values[1]	auto[1]	auto[0]	auto[1]	42	1		T21	2		T16	1		T24	2
all_values[1]	auto[1]	auto[1]	auto[1]	37	1		T22	1		T23	1		T71	1
all_values[2]	auto[0]	auto[0]	auto[0]	29	1		T26	2		T23	1		T77	1
all_values[2]	auto[0]	auto[0]	auto[1]	38	1		T21	2		T22	2		T73	3
all_values[2]	auto[0]	auto[1]	auto[0]	15	1		T26	2		T23	3		T72	1
all_values[2]	auto[0]	auto[1]	auto[1]	40	1		T16	3		T24	3		T25	1
all_values[2]	auto[1]	auto[0]	auto[1]	37	1		T21	1		T16	1		T22	1
all_values[2]	auto[1]	auto[1]	auto[1]	42	1		T21	1		T22	1		T25	1
all_values[3]	auto[0]	auto[0]	auto[0]	20	1		T21	1		T24	1		T71	1
all_values[3]	auto[0]	auto[0]	auto[1]	40	1		T22	1		T26	2		T25	1
all_values[3]	auto[0]	auto[1]	auto[0]	11	1		T21	1		T26	1		T23	2
all_values[3]	auto[0]	auto[1]	auto[1]	47	1		T21	1		T16	1		T22	1
all_values[3]	auto[1]	auto[0]	auto[1]	50	1		T16	2		T22	2		T23	1
all_values[3]	auto[1]	auto[1]	auto[1]	33	1		T21	1		T16	1		T24	1
all_values[4]	auto[0]	auto[0]	auto[0]	14	1		T16	1		T26	1		T71	1
all_values[4]	auto[0]	auto[0]	auto[1]	35	1		T16	1		T22	1		T26	1
all_values[4]	auto[0]	auto[1]	auto[0]	6	1		T71	1		T78	2		T80	1
all_values[4]	auto[0]	auto[1]	auto[1]	54	1		T21	1		T16	1		T24	3
all_values[4]	auto[1]	auto[0]	auto[1]	50	1		T21	1		T16	1		T22	3
all_values[4]	auto[1]	auto[1]	auto[1]	42	1		T21	2		T26	1		T23	2
all_values[5]	auto[0]	auto[0]	auto[0]	27	1		T21	1		T16	2		T23	2
all_values[5]	auto[0]	auto[0]	auto[1]	49	1		T21	2		T22	1		T24	2
all_values[5]	auto[0]	auto[1]	auto[0]	9	1		T16	2		T81	3		T82	2
all_values[5]	auto[0]	auto[1]	auto[1]	37	1		T24	1		T25	1		T71	1
all_values[5]	auto[1]	auto[0]	auto[1]	46	1		T22	3		T24	1		T26	1
all_values[5]	auto[1]	auto[1]	auto[1]	33	1		T21	1		T23	1		T77	3
all_values[6]	auto[0]	auto[0]	auto[0]	32	1		T21	2		T22	2		T26	1
all_values[6]	auto[0]	auto[0]	auto[1]	46	1		T21	1		T16	3		T24	1
all_values[6]	auto[0]	auto[1]	auto[0]	16	1		T25	2		T74	1		T75	1
all_values[6]	auto[0]	auto[1]	auto[1]	41	1		T22	1		T24	2		T26	2
all_values[6]	auto[1]	auto[0]	auto[1]	38	1		T21	1		T16	1		T24	1
all_values[6]	auto[1]	auto[1]	auto[1]	28	1		T22	1		T23	2		T77	1
all_values[7]	auto[0]	auto[0]	auto[0]	27	1		T21	1		T16	3		T23	1
all_values[7]	auto[0]	auto[0]	auto[1]	41	1		T21	2		T24	2		T26	2
all_values[7]	auto[0]	auto[1]	auto[0]	11	1		T16	1		T22	1		T71	1
all_values[7]	auto[0]	auto[1]	auto[1]	41	1		T22	1		T23	1		T25	2
all_values[7]	auto[1]	auto[0]	auto[1]	44	1		T22	1		T24	2		T26	1
all_values[7]	auto[1]	auto[1]	auto[1]	37	1		T21	1		T22	1		T26	1
all_values[8]	auto[0]	auto[0]	auto[0]	23	1		T22	3		T74	1		T75	3
all_values[8]	auto[0]	auto[0]	auto[1]	48	1		T16	1		T24	1		T25	3
all_values[8]	auto[0]	auto[1]	auto[0]	10	1		T22	1		T23	1		T72	1
all_values[8]	auto[0]	auto[1]	auto[1]	44	1		T21	2		T24	2		T26	2
all_values[8]	auto[1]	auto[0]	auto[1]	43	1		T21	1		T16	2		T24	1
all_values[8]	auto[1]	auto[1]	auto[1]	33	1		T21	1		T16	1		T26	1
all_values[9]	auto[0]	auto[0]	auto[0]	18	1		T22	1		T24	1		T73	1
all_values[9]	auto[0]	auto[0]	auto[1]	45	1		T21	2		T16	1		T22	1
all_values[9]	auto[0]	auto[1]	auto[0]	4	1		T76	1		T83	1		T84	1
all_values[9]	auto[0]	auto[1]	auto[1]	48	1		T16	1		T24	1		T25	1
all_values[9]	auto[1]	auto[0]	auto[1]	48	1		T21	2		T16	1		T22	1
all_values[9]	auto[1]	auto[1]	auto[1]	38	1		T16	1		T22	1		T24	2
all_values[10]	auto[0]	auto[0]	auto[0]	20	1		T22	2		T71	2		T77	1
all_values[10]	auto[0]	auto[0]	auto[1]	36	1		T21	1		T16	1		T24	1
all_values[10]	auto[0]	auto[1]	auto[0]	14	1		T22	2		T23	2		T71	1
all_values[10]	auto[0]	auto[1]	auto[1]	47	1		T21	1		T16	1		T24	2
all_values[10]	auto[1]	auto[0]	auto[1]	49	1		T21	2		T16	2		T24	1
all_values[10]	auto[1]	auto[1]	auto[1]	35	1		T26	1		T25	1		T77	1
all_values[11]	auto[0]	auto[0]	auto[0]	27	1		T24	1		T23	3		T73	1
all_values[11]	auto[0]	auto[0]	auto[1]	41	1		T16	1		T26	1		T25	1
all_values[11]	auto[0]	auto[1]	auto[0]	16	1		T23	1		T73	1		T78	1
all_values[11]	auto[0]	auto[1]	auto[1]	37	1		T21	2		T22	2		T24	1
all_values[11]	auto[1]	auto[0]	auto[1]	49	1		T21	1		T16	1		T24	2
all_values[11]	auto[1]	auto[1]	auto[1]	31	1		T21	1		T16	2		T22	2
all_values[12]	auto[0]	auto[0]	auto[0]	24	1		T25	1		T77	1		T74	1
all_values[12]	auto[0]	auto[0]	auto[1]	44	1		T21	1		T16	1		T22	2
all_values[12]	auto[0]	auto[1]	auto[0]	13	1		T72	1		T74	1		T75	2
all_values[12]	auto[0]	auto[1]	auto[1]	44	1		T24	1		T26	2		T23	2
all_values[12]	auto[1]	auto[0]	auto[1]	38	1		T21	3		T16	1		T24	1
all_values[12]	auto[1]	auto[1]	auto[1]	38	1		T16	2		T22	2		T24	1
all_values[13]	auto[0]	auto[0]	auto[0]	28	1		T21	1		T16	1		T25	1
all_values[13]	auto[0]	auto[0]	auto[1]	45	1		T21	1		T22	1		T26	2
all_values[13]	auto[0]	auto[1]	auto[0]	15	1		T77	1		T74	1		T75	1
all_values[13]	auto[0]	auto[1]	auto[1]	36	1		T16	1		T22	2		T24	2
all_values[13]	auto[1]	auto[0]	auto[1]	48	1		T21	1		T16	1		T24	1
all_values[13]	auto[1]	auto[1]	auto[1]	29	1		T21	1		T16	1		T22	1
all_values[14]	auto[0]	auto[0]	auto[0]	19	1		T26	4		T25	1		T72	2
all_values[14]	auto[0]	auto[0]	auto[1]	42	1		T16	2		T22	2		T23	1
all_values[14]	auto[0]	auto[1]	auto[0]	11	1		T72	2		T78	2		T79	1
all_values[14]	auto[0]	auto[1]	auto[1]	46	1		T21	3		T22	1		T24	1
all_values[14]	auto[1]	auto[0]	auto[1]	49	1		T21	1		T16	1		T24	1
all_values[14]	auto[1]	auto[1]	auto[1]	34	1		T16	1		T22	1		T24	2
all_values[15]	auto[0]	auto[0]	auto[0]	26	1		T16	1		T22	3		T24	2
all_values[15]	auto[0]	auto[0]	auto[1]	31	1		T21	1		T24	1		T71	1
all_values[15]	auto[0]	auto[1]	auto[0]	6	1		T22	1		T23	1		T25	1
all_values[15]	auto[0]	auto[1]	auto[1]	46	1		T16	1		T26	2		T25	1
all_values[15]	auto[1]	auto[0]	auto[1]	47	1		T21	3		T16	1		T24	1
all_values[15]	auto[1]	auto[1]	auto[1]	45	1		T16	1		T26	1		T25	1
all_values[16]	auto[0]	auto[0]	auto[0]	16	1		T16	1		T26	1		T77	1
all_values[16]	auto[0]	auto[0]	auto[1]	57	1		T21	2		T16	1		T22	1
all_values[16]	auto[0]	auto[1]	auto[0]	7	1		T26	1		T23	1		T72	2
all_values[16]	auto[0]	auto[1]	auto[1]	39	1		T16	1		T24	1		T26	1
all_values[16]	auto[1]	auto[0]	auto[1]	58	1		T21	2		T24	1		T23	1
all_values[16]	auto[1]	auto[1]	auto[1]	24	1		T16	1		T22	3		T26	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal